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ON THE CIRCUIT ORIENTED AVERAGE LARGESIGNAL
MODELING OF SWITCHING POWER CONVERTERS AND
ITS APPLICATIONS
Carlos Eduardo Cuadros Ortiz
Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State
University in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
in
Electrical Engineering
Dushan Boroyevich, Chairman
Douglas Lindner
Jacobus Van Wyk
Ricardo Burdisso
Virgilio Centeno
William Baumann
August 8, 2003
Blacksburg, Virginia
Keywords: average modeling, slow dynamics manifold, PWM converters, ZVS and
ZVZCS fullbridge converters, softswitched threephase buck rectifier, space vector
modulation.
ON THE CIRCUIT ORIENTED AVERAGE LARGESIGNAL
MODELING OF SWITCHING POWER CONVERTERS AND
ITS APPLICATIONS
Carlos Eduardo Cuadros Ortiz
ABSTRACT
A systematic and versatile method to derive accurate and efficient Circuit
Oriented Large Signal Average Models (COLSAMs) that approximate the slow dynamics
manifold of the moving average values of the relevant state variables for PulseWidth
Modulated (PWM) dc to dc and threephase to dc power converters is developed. These
COLSAMs can cover continuous conduction mode (CCM) as well as discontinuous
conduction mode (DCM) of operation and they are over one order of magnitude cheaper,
computation wise, than the switching models. This method leads primarily to simple and
effective inputoutput oriented models that represent transfer as well as loading
characteristics of the converter. Sine these models consist of time invariant continuous
functions they can be linearized at an operating point in order to obtain smallsignal
transfer functions that approximate the dynamics of the original PWM system around an
orbit.
The models are primarily intended for software circuit simulators (i.e. Spice
derived types, Saber, Simplorer, etc), to take advantage of intrinsic features such as
transient response, linearization, transfer function, harmonic distortion calculations,
without having to change simulation environment. Nevertheless, any mathematics
simulator for ordinary differential equations can be used with the set of equations
obtained through application of Kirchoff’s laws to the COLSAMs. Furthermore, the
COLSAMs provide physical insight to help with power stage and control design, and
they allow easy interconnection among themselves, as well as with switching models, for
complete analysis at different scales (time, signal level, complexity; interconnectivity).
A new average model for the ZeroVoltage Switched FullBridge (ZVSFB)
PWM Converter is developed with the above method and its high accuracy is verified
with simulations from a switching behavioral model for several circuit component values
for both CCM and DCM.
Intrinsic positive damping effects and special delay characteristics created by an
energy holding element in a saturable reactorbased ZeroVoltage ZeroCurrent Switched
FullBridge (ZVZCSFB) PWM converter are explained for the first time by a new
average model. Its large signal predictions match very well those from switch model
simulations whereas its smallsignal predictions are verified with experimental results
from 3.5 kW prototype modules. The latter are used in a multimodule converter to
supply the DC power bus in and aircraft. The design of control loops for the converter is
based on the new model and its linearization.
The ZVZCSFB PWM converter’s average model above is extended to deal with
interconnection issues and constraints in a QuasiSingle Stage (QSS) ZeroVoltage ZeroCurrent Switched (ZVZCS) ThreePhase Buck Rectifier. The new model reveals strong
nonlinear transfer characteristics for standard Space Vector Modulation (SVM), which
lead to high input current distortion and output voltage ripple inadmissible in
telecommunications applications. Physical insight provided by this average model led to
the development of a combined modified SVM and feedforward dutycycle
compensation scheme to reliably minimize the output voltage ripple. Experimental results
from a 6 kW prototype validate large signal model for standard and modified SVM, with
and without dutycycle compensation scheme.
ACKNOWLEDGEMENTS
I would like to express my sincere appreciation to my advisor, Prof. Dushan
Boroyevich, for his guidance, encouragement, patience and support through the course of
this work.
I also wish to thank Profs. William Baumann, Ricardo Burdisso, Virgilio
Centeno, Douglas Lindner and, Jacobus van Wyk for their contributions and suggestions
as members of my committee.
Special thanks are due to my fellow classmates Sriram Chandrasekaran and
Kunrong Wang for writing the control program, designing and building the prototype and
discussing technical issues for the threephase rectifier. Without their help, this work
would not have been possible.
In addition, I would like to thank all the faculty, staff and students at CPES for all
their support, collaboration and friendship.
iv
To
Ligia,
Maria Fernanda
and
Miguel Eduardo
Table of Contents
1. INTRODUCTION.……………………………………………………………1
1.1. Motivation and Goals…………………………………………………………...1
1.2. Literature Review……………………………………………………………….2
1.3. Dissertation Outline and Major Results………………………………………6
2. MATHEMATICALDESCRIPTION OF SWITCHING POWER
CONVERTERS AND THEIR LARGE SIGNAL AND SMALLSIGNAL MODELING………………………………………………………..9
2.1. Characteristics and StateSpace Description of PWM Converters………….9
2.1.1. Continuoustime statespace equations……………………………….…...9
2.1.2. Sampleddata statespace equations……………………………………...11
2.1.3. Sampleddata modeling of a simple PWM converter……………….…...12
2.2. Generalized Method of Averaging for PWM Converters……………..…….18
2.2.1. Procedures of the method………………………………………….….….19
2.2.2. Illustration of the generalized method of averaging for a simple
PWM Converter………………………………………………………….20
2.2.3. Generalized method of averaging for the open loop buck converter….…23
2.3. Averaging Method for TwoTime Scale PWM Converters…………………24
2.3.1. Statespace description for twotime scale PWM converters……………24
2.3.2. Practical procedure for the method………………………………………25
2.4. Synthesis Method for Averaged Circuit Models of PWM Converters…......26
2.4.1. In placeaveraging……………………………………………………..…26
2.4.2. PWM switch equivalent circuits…………………………………………29
2.5. Analysis of Strengths and Weaknesses of these Methods…………………...30
2.6. A New Procedure for Averaged Circuit Models…………………………..…34
2.6.1. Philosophy of the new average modeling procedure………………….…34
2.6.2. Steps of the new average modeling procedure and their guidelines…..…35
2.6.3. Application of the new procedure to the buck converter……………...…36
2.6.4. Model verification and comments…………………………………….…40
3. MODELING OF THE ZVSFB PWM CONVERTER……………….…..58
3.1. ZVSFB Converter Operation………………………………..……………….58
3.1.1. CCM operation…………………………………………….………….…58
3.1.2. DCM operation…………………………………………………………..53
3.2. New Averaged Circuit Model for the ZVSFB Converter………………..…64
3.2.1. Step 1: Fast/slow classification of state variables……………………..…64
3.2.2. Step 2: LTI input/output parts……………………………………………65
3.2.3. Step 3:“Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network………………...65
3.2.4. Step 4: Calculation of onecycle average for the variables in the
previous step…………………………………………………………….65
3.2.5. Step 5: Calculation of algebraic constraints……………………………..67
vi
3.2.6. Step 7: Implementation of circuit oriented simulation…………………..67
3.3. Previous Average Models for the ZVSFB Converter……………………….68
3.4. Simulation Results……………………………………………………………..68
3.4.1. Transient simulations for parameter set 1………………………………..68
3.4.2. Transient simulations for parameter set 2………………………………..69
3.4.3. Transient simulations for parameter set 3………………………………..69
3.4.4. Transient simulations for parameter set 4………………………………..70
3.4.5. Transient simulations for parameter set 5………………………………..71
3.4.6. Transient and smallsignal simulations results…………………………..71
4. MODELING OF THE SATURABLE INDUCTOR BASED
ZVZCSFBPWM DCDC CONVERTER………………………………...93
4.1. ZVZCSFBPWM Converter Operation……………………………………..93
4.1.1. CCM operation………………………………………………………..….93
4.1.2. DCM operation…………………………………………………………..99
4.2. New Average Circuit Model for the ZVZCSFB Converter…………….....100
4.2.1. Step 1: Fast/slow classification of state variables………………………100
4.2.2. Step 2: LTI input/output parts…………………………………………..102
4.2.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network………………...102
4.2.4. Step 4: Calculation of onecycle average for the variables in the
Previous step……………………………………………………………102
4.2.5. Step 5: Calculation of algebraic constraints…………………………….105
4.2.6. Step 7: Implementation of circuit oriented simulation…………………105
4.2.7. Identification and modeling of energy holding elements in fast
dynamic subsystems…………………………………………………….105
4.3. Simulation Results……………………………………………………………112
4.3.1. Transient simulations for parameter set 1………………………………112
4.3.2. Transient simulations for parameter set 2………………………………117
4.3.3. Transient simulations for parameter set 3………………………………117
4.3.4. Transient simulations for parameter set 4………………………………117
4.3.5. Transient simulations for parameter set 5………………………………125
4.3.6. Transient simulations for parameter set 6………………………………125
4.4. Dynamics Comparison among Buck, ZVSFB and ZVZCSFB
Converters ……………………………………………………………………125
4.4.1. Transient response and smallsignal transfer function from new
average model and its linearization…………………………………….125
4.4.2. Smallsignal experimental results………………………………………126
5. MODELING AND MODULATION SCHEME FOR QSSZVZCS
THREEPHASE BUCK RECTIFIER……………………………………136
5.1. ThreePhase Buck Rectifier………………………………………………….136
5.1.1. Threephase buck rectifier averaged model…………………………….142
5.1.2. Threephase buck rectifier with singleloop control……………………145
5.1.3. Modified SVM (swapping)……………………………………………..145
5.2. QSSZVZCS ThreePhase Buck Rectifier Operation……………………...145
vii
5.2.1. Threephase buck rectifier and ZVZCSFB converter synchronization..145
5.2.2. QSSZVZCS threephase buck rectifier operation with standard SVM..145
5.2.3. Topological stages and analytical description………………………….147
5.3. New Average Circuit Model for the QSSZVZCS Rectifier………...153
5.3.1. Step 1: Fast/slow classification of state variables………………………153
5.3.2. Step 2: LTI input/output parts…………………………………………..153
5.3.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network………………...153
5.3.4. Step 4: Calculation of onecycle average for the variables in the
previous step……………………………………………………………153
5.3.5. Step 5: Calculation of algebraic constraints…………………………….157
5.3.6. Step 7: Implementation of circuit oriented simulation…………………157
5.3.7. Modeling of energy holding elements in fast dynamic subsystems……157
5.4. Analysis of Variable Distortion……………………………………….160
5.5. Hardware Implementation……………………………………………160
5.5.1. Implementation of digital controller……………………………..161
5.5.2. Implementation of decoder logic………………………………...161
5.6. Software Implementation……………………………………………...164
5.6.1. Synchronization with input voltages……………………………………164
5.7. Compensation Scheme for Standard SVM………………………………….164
5.8. Compensation Scheme for Modified SVM…………………………...170
5.9. Compatibility of Modified SVM and Compensation Scheme with
Single Input Control
Strategy…………………………………………………………………173
6. CONCLUSIONS……………………………………………………………176
7. REFERENCES……………………………………………………………..178
A Saber Template and Schematics for Buck Converter………………..….194
B Saber Templates for ZVSFB Converter Average Models………….…..197
C Analysis and Design Procedure for Saturable ReactorBased
ZeroVoltage ZeroCurrent Switched, FullBridge Converter
and Saber Template for its Average Model……………………………….202
D Modified Equations for Cases 2 and 3 of QSSZVZCS ThreePhase
Buck Rectifier Operation and for Compensated First DutyCycle for
Case 1 ……………………………………………………………………….224
VITA……………………………………………………………………………229
viii
LIST OF FIGURES
2.1.
PWM converter structure………………………………………………………...10
2.2
Simple buck PWM converter with current feedbac……………………………...14
2.3. Buck converter circuit topologies………………………………………………..15
2.4
Relevant waveforms for dutycycle calculation…………………………………16
2.5. Partition of PWM converter structure……………………………………………31
2.6.
The PWM switch………………………………………………………………...32
2.7.
PWMswitch equivalent average circuit………………………………………....33
2.8.
Starting point for new average modeling procedure……………………………..41
2.9.
Step 1: Slow/fast variables separation……………….…………………………..42
2.10. Step 2: Identification of Linear Time Invariant input/output parts..…….……….43
2.11. Step 3: Identification of “dependent” variable drawn from input and
“independent” variable delivered to output LTI parts……………….….……….44
2.12. Step 4: Calculation of controlled source onecycle average……………………..45
2.13. Step 5: Calculation of algebraic constraints……………………….……………..46
2.14. Step 6: Incorporation of feedback loop….……………………………………….47
2.15. Step 7: implementation of circuit simulator oriented average model……………48
2.16. Average circuit model for buck converter in CCM operation …………………..49
2.17. Buck converter in DCM operation……………………………………………….50
2.18. Average circuit model for buck converter in DCM …......………………………51
2.19. Average circuit models for buck converter in CCM and DCM operation……….52
2.20. Input/output structure average circuit models for buck converter in CCM and
DCM operation ………………………………………………………………….53
2.21. Analog computation of d2……………….…………………………………….…54
2.22. Analog computation of d and d2 with feedback loop…………………………….55
2.23. Simulation results from average (reddashed) and switch (greensolid) mode.
Top: duty ratios, middle: inductor current, bottom: output voltage………….…..56
2.24. Simulation results from average (reddashed) and switch (greensolid) mode….57
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
3.9.
ZVSFB PWM converter…………………………….…………….…………….60
Typical ZVSFB PWM converter waveforms in CCM………………………….61
Typical ZVSFB PWM converter waveforms in DCM…………………….……65
ZVS converter equivalent average models and waveforms in CCM…….………72
ZVS converter equivalent average model and waveforms in DCM……………..73
Analog schematic for computation of Dtrf and D2………….……………………74
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average(black) models for parameter
set 1 with zero initial state for all models………………………………………..75
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 1 with zero initial state for all models………………………..…...76
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter
set 1 with zero initial state for all models……………………..…………………77
ix
3.10.
3.11.
3.12.
3.13.
3.14.
3.15.
3.16.
3. 17.
3.18.
3.19.
3.20.
3.21.
3.22.
3.23.
3.24.
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 1 with zero initial state for all models…………………………….78
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 2 with zero initial state for all models………………...…………..79
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 2 with zero initial state for all models…………………………….80
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 2 with zero initial state for all models……………..……………..81
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 3 with zero initial state for all models…………………..………...82
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 3 with zero initial state for all models………………….…………83
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 3 with zero initial state for all models…………………………….84
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 4 with zero initial state for all models…………………………….85
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 4 with zero initial state for all models…………………………….86
Duty ratios (top), filter inductor current (middle) and capacitor voltage
(bottom) from switching (green), new average (pink) and previous average
(black) models for parameter set 5 with zero initial state for all models………...87
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 5 with zero initial state for all models…………………………….88
Capacitor voltage (top) and filter inductor current (bottom) transient response
from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set I ………………………………..………..89
Capacitor voltage (top) and filter inductor current (bottom) transfer functions
from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set I …………………………………………90
Capacitor voltage (top) and filter inductor current (bottom) transient response
from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set II ………………………………...………91
Capacitor voltage (top) and filter inductor current (bottom) transfer functions
from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set II.……………………………………..….92
x
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
4.10.
4.11.
4.12.
4.13.
4.14.
4.15.
4.16.
4.17.
4.18.
4.19.
ZVZCS converter………………………………………………………………...94
ZVZCSFB PWM primary and filter inductor current waveforms in CCM…….96
ZVZCSFB PWM primary and filter inductor current waveforms in DCM...…..98
ZVZCS converter equivalent average models and waveforms in CCM………..101
Calculation of average blocking capacitor voltage……………………………..103
Analog computation of Dtrf and D2………………….…………………………106
Analog implementation of dynamic relationship between filter inductor
current an blockingcapacitor peak voltage ……………………………………107
Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), first average (blue) and second average (pink) models for parameter
set 1 with zero initial state for all models……………………………...……….109
Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter
set 1 with zero initial state for all models…………………..…………………..110
Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter
set 1 with zero initial state for all models………………………………………111
Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 1 with zero initial state for all models………………………………………113
Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero
initial state for all models ………………………………..…………………….114
Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero
initial state for all models ………………………………..……………………..115
Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero
initial state for all models ………………………………..……………………..116
Whole transient of filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 2
with zero initial state for all models.………………………………..…………..118
Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 2 with zero
initial state for all models ………………………………..……………………..119
Whole transient of filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 3
with zero initial state for all models ………………………………..…………..120
Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero
initial state for all models ………………………………..……………………..11
Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero
initial state for all models……………………………………………………….122
xi
4.20. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 4 with zero initial state for all models………………………………………123
4.21. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 4 with zero
initial state for all models ……………………………………….……………...124
4.22. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 5 with zero initial state for all models………………………………………127
4.23. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 5 with zero
initial state for all models …………………………………………………...….128
4.24. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 6 with zero initial state for all models……………………………...……….129
4.25. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 6 with zero
initial state for all models ……………………………………………...130
4.26. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVSFB (blue) and
ZVZCSFB (black) converters with parameter set I……………………………131
4.27. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red),
ZVSFB (blue) and ZVZCSFB (black) converters with parameter set I………132
4.28. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVSFB (blue)
and ZVZCSFB (black) converters with parameter set II ……………………...133
4.29. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red),
ZVSFB (blue) and ZVZCSFB (black) converters with parameter set II……..134
4.30. Experimental control to capacitor voltage (top) transfer for Buck and
ZVZCSFB converters with parameter set II ………………………………….135
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
QSSZVZCS threephase rectifier………….…………………………………..137
Threephase buck rectifier and electric sectors…………………………………138
Threephase buck rectifier with standard SVM ………………………....……..140
Threephase buck rectifier ideal SVM operation ………………….…………...141
Threephase buck rectifier average model structure………………………..…..143
Threephase buck rectifier SVM with and without swapping…………………144
Synchronization between threephase buck rectifier and ZVZCSFB
converter………………………………………………………………………..146
5.8.
QSSZVZCS rectifier typical waveforms and switch structures……………….148
5.9.
QSSZVZCS PWM rectifier average model structure………………………….150
5.10. Calculation of average blocking capacitor voltage……………………….…….152
5.11. QSSZVZCS rectifier desired and experimental waveforms with typical
SVM operation…………………..……………………………………………..154
xii
5.12. QSSZVZCS rectifier equivalent primary and secondary dutycycles cases
with typical SVM operation……………………...……………………………..155
5.13. Threephase buck rectifier (solid) and QSSZVZCS rectifier simulated
effective (dashed) primary and secondary dutycycles for whole line cycle
with SVM……………………………………………………………………….158
5.14. Normalized QSSZVZCS rectifier simulated and experimental dutycycles, compensation with SVM and phase voltage …………………………...159
5.15. QSSZVZCS rectifier openloop experimental phase voltage and currents
and output voltage ripple with SVM, before and after compensation for
360V peak line voltage, 48V output voltage and 40A load current…………….162
5.16. Control block diagram…………………………….……………………………163
5.17. QSSZVZCS rectifier power stage for 208380V line voltage, 48V output
voltage, 6 kW output power and 40 kHz switching frequency…………………165
5.18. QSSZVZCS rectifier closedloop experimental phase voltage and currents
and output voltage ripple with SVM, before and after compensation for
360V peak line voltage, 48V output voltage and 40A load current…………….166
5.19. QSSZVZCS rectifier simulated and experimental dutycycles and
compensation with modified (dutycycle order swapping) SVM………………168
5.20. QSSZVZCS rectifier phase currents and secondary rectifier voltage at
swapping border (phase voltage crossing) with modified SVM ……………….169
5.21. QSSZVZCS rectifier openloop experimental output voltage ripple, phase
current and voltage with modified SVM, before and after compensation
for 360V line voltage, 48V output voltage and 40A load current …….……….171
5.22. QSSZVZCS rectifier closedloop experimental output voltage ripple,
phase current and voltage with modified SVM, after compensation for
360V line voltage, 48V output voltage and 40A load current………………….172
5.23. QSSZVZCS rectifier closedloop response to step load disturbance
(1.6 Ohm load switched in) with swapping and compensated duty cycles
for 380V peak line voltage, 48V output voltage and 1.1 Ohm initial load……..174
5.24. QSSZVZCS rectifier closedloop response to step load disturbance
(1.0 Ohm load switched in) with swapping and compensated duty cycles
for 380V peak line voltage, 48V output voltage and 1.1 Ohm initial load……..175
xiii
LIST OF TABLES
1.
2.
3.
4.
Parameter value sets for transient response of ZVSFB converter.……………...68
Parameter value set I for smallsignal model and transient response of Buck,
ZVSFB and ZVZCSFB converters…………………………….………………69
Parameter value set II for smallsignal model and transient response of Buck,
ZVSFB and ZVZCSFB converters…………………………………………….70
Parameter set values for transient simulations …………………………………112
xiv
1.
INTRODUCTION
1.1.
Motivation and Goals
Switching power converters have become ubiquitous in consumer products as
well as in industrial, medical, and aerospace equipment due to their high efficiency, low
volume and weight, fast dynamic response, and low cost. Even though extensive efforts
and resources are continuously devoted to new component technologies and converter the
development of versatile modeling techniques suitable for general switching power
converters is still lagging.
This dissertation aims at reducing that gap by providing a systematic approach to
the development of accurate and computationally efficient but still intuitively simple
circuit oriented, average largesignal models for pulsewidth modulated (PWM) fullbridge (FB) derived, dc to dc and threephase to dc power converters. Since a large
number of new converter topologies based on these structures have emerged lately,
versatile and reliable models are needed to speed up exploitation of their full potential.
The objectives of the circuit oriented, continuoustime, largesignal average
models developed here are, besides allowing very fast simulation times and reduced
memory space with respect to discrete and switching models, to gain physical insight, to
guarantee complete representation of large and smallsignal behavior and to overcome
limitations of existing average models by including discontinuous conduction mode
(DCM) and continuous conduction mode (CCM) operation and storage element effects in
the form of algebraic and/or dynamic constraints to handle large and asymmetric ripple
components as well as feedback loops. This approach makes the new models very useful
in large signal analysis and design of singlestage single and multimodule converters, as
well as multistage converters, together with their respective input and output filters. In
addition, the new models can be linearized at an operating point to derive a smallsignal
model that closely approximates the behavior around an orbit for the original system, and
hence, provides a solid starting point for control design. As a result, thorough studies of
1
interaction effects and tradeoffs amongst power stage(s) and filter(s) structures, current
and voltage ripple, harmonic distortion, modulation scheme, control loop(s), stability,
transient response, to name a few, can be conducted.
The systematic modeling procedure allows for easy adaptation of the models to
perform analyses at different scales, such as time, signal level, complexity,
interconnectivity. Model extension for hybrid simulation, i.e. mixing of average and
switching models, can be easily carried out to accelerate analysis of specific subsystems
in multistage and/or multimodule converters.
Even though the new circuit oriented average models can be used with any
commercial mathematics software that allows simulation of ordinary differential
equations, one of the major motivations for this work is to take advantage of common
features in commercial circuit simulators, i.e. transient response, linearization, transfer
function, harmonic distortion calculations; to help with power converters analysis and
design issues without having to change simulation environment.
1.2.
Literature Review
Most of the references mentioned in this work have excellent reference lists
therein, which are also assumed referenced and that are omitted here for compactness.
Switching power converters can be mainly classified according to the type of
input (ac or dc) and output (ac or dc) variables [E5, M7]. Further classifications with
respect to parameters such as control variable, PWM, or frequency modulation, [E5, M7],
waveform, i.e. piece wise linear or resonant [E5, M7], switching stresses, i.e. hard or soft
[E5, J4, M7, H3, V6, V7], among others, are well known.
Most common PWM power converters have switch transitions determined by
control and state variables through constraint equations [B6, B11, B12, C5, C7, C8, C20,
2
E1, E3, E5, F1, G1, H6, K7, L2, M7, O3, S4, T8, V3, X2], and in between those
transitions the converters are very accurately described by linear autonomous ordinary
differential equations. Sampleddata models [A1, B6, B12, F1, G1, G3, H4, L2, L13,
L15, M5, P1, T7, V3, V4] are suitable to represent and to simulate these converters at
switching instants, but they lack information between samples and are computationally
expensive. However, the closedloop operation can be accurately described and
characterization (Poincare maps) of iterative maps for instability, bifurcation and chaotic
behavior analysis can be easily obtained [A2, B2, C3, C17, D1, F4, H1, J1, L3, P4, S24,
T3]. Large signal stability of PWM and quasiresonant converters through nonlinear
modeling and control has also been discussed in [C4, C17, E3, F2, G3, H6, L17, S18,
S19]. From all of these large signal approaches, continuoustime smallsignal models can
be obtained through linearization around a periodic trajectory (orbit). When the starting
model is discrete subsequent transformation of the results into continuous time is needed
[F1, F3, L2, S17, T7, V3, W5].
Smallsignal models have also been obtained from very dissimilar perspectives
such as model fitting with neural networks of data from converter simulations [H5, L7],
analytical approximations [E2, V11, W4], and perturbation of exponential transition
matrices either on computer [M4, W5] or on state plane graphs [O4].
The wellknown statespace averaging method [B11] can also be developed as
the loworder approximation in several different methods by retaining only the first terms
in:
(a) power series for the matrix exponentials in the sampledata modeling [V3],
(b) multifrequency averaging [C1],
(c) the generalized method of averaging [K6, L4, L6, N3, S2, S13, V3, W3].
It provides information about the average of the state variables, but loses
accuracy in the high frequency range, i.e. near a half of the switching frequency, and/or
when the filter time constants are close to the switching period, as it usually happens in
some of the sampleddata models above. Similar characteristics with slight result
3
improvements are exhibited by the current injectionabsorption method [K5], by the
averaged PWMswitch model [V8] and its several extensions for multiswitch PWM
converters and resonant converters, and by several other circuitoriented average models
[A3, C5, C6, C7, C24, E4, J5, L9, L11, K4, M2, M6, N2, R1, O1, O2, R1, S4, S6, S7, S8,
S20, T4, T8, V1, V8, V9, V10, W3, W7, X2, X4, Y2].
Validity of the method of averaging to simple PWM converter topologies was
rigorously proved [B3, K6, L4, S2] and extended to provide frequencydependent
continuoustime average models for open and closedloop operation [B5, L5, L6].
Unfortunately, application of this technique or the familiar stateplane portrait methods
[G2, O3, S10], useful to analyze operation of low order resonant converters, to more
complex softswitched power converters becomes almost intractable. Analytic
approximations and modifications to the method of averaging have also been proposed
for PWM and some types of resonant converters [N3, S13, S14, S22, W3, X3].
Extended describing functions and multifrequency methods [C1, C18, S3, Y1]
overcome this tractability problem and had been proven useful in smallsignal analysis of
resonant and multiresonant converters of any order, despite their lack of physical insight
and the need for special software.
Some special simulator programs and/or algorithms have been developed to
provide shorter simulation times [B6, B7, L8, M1, N1, P2, S5, T2, D2, B9, B10] at the
expense of limited functionality and data preparation.
Following the attempt made in [R4], a corrected and general continuoustime,
statespace, smallsignal model of current programmed PWM converters was developed
in [T5, T7] and verified with the so called exact smallsignal models obtained by
application of time varying transfer functions [T6, T9]. However none of these papers
discusses relevance of time varying effects at frequencies near a half of the switching
frequency which are detailed in [P3] and analyzed for threephase PWM modulators in
4
[H2]. The same happens in [K5, S16, S21, S24, T1, V8, V10] where attempts to fit and/or
explain smallsignal measurements in the high frequency range were made without
dealing with the stochastic characteristics of those measurements. Furthermore, extensive
similar work on smallsignal modeling of the modulator and/or the whole converter for
peak and average current control has been reported in [B8, C19, K1, K8, L10, P5, R5,
S23, S24, T1, X1].
Geometrical linearization through graphical analysis of perturbed steadystate
waveforms was used in [V5] to provide an approximate smallsignal model of the widely
used ZeroVoltage Switched, FullBridge (ZVSFB) PWM converter [S1] based on the
PWM switch model. An approximate large signal model whose usage is restricted to a
narrow range in CCM and a smallsignal model derivation along the lines of [S1] for the
ZVSFB converter was presented in [T4]. Similarly smallsignal models for some ZVS
and ZeroVoltage ZeroCurrent Switched FullBridge ZVZCSFB converters are
developed in [C15, X5].
Lately, with the progress in symbolic math packages, methods to obtain closed
form expressions for large and smallsignal models of PWM converters have been
developed [B4, S12]. These methods separate fast and slow dynamic subsystems in the
converter and describe their interaction through an algebraic equation. However, they do
not allow for nonlinear or energy holding components in the fast dynamic subsystem or
high order systems for which closed form solutions cannot be computed. Therefore they
cannot be applied to many new softswitched topologies [B1, C9, C10, C11, C12, C16,
J2, J3, J4, K2, K3, L1, L12, L14, M3, V6, V7, W1, W2, W6, X5].
From a different perspective, power transfer based models [S7, S8, E5] provide
good low frequency description of inputoutput characteristics for certain PWM
converters when lossless switching devices are considered. When losses are included,
the principle of energy conservation needs to be invoked [C24]. These approaches, when
combined with other models such as current injectionabsorption, statespace averaging,
5
PWM and resonant switch, are useful in model verification as well as in calculation of
input and output impedances for subsystem interaction analysis [C13, G2, R3].
A few attempts to develop a SPICE oriented dual model to deal both with CCM &
DCM were plagued with convergence problems [C7, G4, S21]. In [R5] the same authors
of [C7] presented a revised version that solved those problems for the buck converter. A
decade later the subject was retaken in [N4] where dual models for most of the simple
PWM converters are presented.
As a matter of completeness the following special modeling approaches are also
mentioned: geometric [S9], phasor transformation [R2], switching flow graph [S11],
virtual winding for transformer magnetizing current [L16].
For the modeling presented here on the threephase buck rectifier and a ZVZCS
threephase to dc converter the wonderful theses [H2, N2] and the references therein
provide all the needed background.
1.3.
Dissertation Outline and Major Results.
1. Mathematical description of large signal average models for switching power
converters. The next chapter reviews analytical procedures for variations of the
generalized method of averaging [K6, S13] proposed for switching power
converters (SPCs). The theoretical foundation behind a method to synthesize
averaged circuits models for SPCs [S4] is also presented. Scope and limitations of
these methods are discussed. A new systematic procedure to derive circuit
oriented average models, which describe inputoutput characteristics for PWM
converters, and that overcomes several of those limitations is developed. This
procedure combines the theoretical foundation of [S4] with variations of some
ideas from inplace circuit averaging techniques in [V8, V9], extensions to
constraints derivation to keep them valid during transient conditions [V3],
6
practices from analog and circuit simulation in order to model CCMDCM
bifurcation [R5] and heuristic guidelines for selecting averaged circuit structure
and relevant states as well as for modeling energy storage components. Basic
features of the new modeling procedure are introduced by applying it to a simple
buck PWM converter. CCM and DCM operation is covered by the same average
model.
2. Modeling of the ZVSFB PWM converter. In Chapter 3 a new and very
accurate average model for both DCM and CCM mode of operation is developed
and its superiority compared to existing models is clearly seen for different
parameter and load values. Smallsignal models obtained through linearization of
the new average model at different operating points show strong positive damping
effects, i.e. intrinsic negative feedback, over the output filter. These results agree
very well with those from experiments.
3. Modeling of a saturable reactorbased ZVZCSFB PWM converter.
Extension of the circuit averaging procedure to include new effects created by a
saturable reactor and a socalled energy holding component, in power converter
modeling literature, provided the only reported model for this ZVZCS converter.
The model, detailed in Chapter 4, explains and recreates the interaction of power
stage components, which leads to negative damping effects, i.e. intrinsic positive
feedback, over the output filter. These effects were also reported for the first time
with the model. Large signal simulation results from the average circuit model
closely match those from a switching model for different parameter and load
values. Smallsignal models from linearization of the average circuit model,
which correctly predicted the negative damping effects seen in transfer function
measurements conducted on 3.5 kW prototypes, were a useful starting point for
currentloop design in a multimodule prototype.
4. Average modeling and modulation scheme development for a QuasiSingle
Stage ZVZCS ThreePhase Buck Rectifier. Chapter 5 illustrates versatility of
7
the modeling procedure when dealing with interconnection issues in this special
multiconverter structure. It is formed by cascading a threephase buck rectifier
and the ZVZCS converter in the previews chapter. Physical insight provided by
the average circuit model developed for this threephase rectifier, which is also a
new result, helped to discover the main causes of strong nonlinear relationships
between commanded dutycycles and effective duty cycles, i.e. voltage transfer
ratio, near the boundaries of the sixtydegree electrical sectors in standard space
vector modulation (SVM). These nonlinearities induced high distortion and ripple
in ac input currents and dc output voltage, which rendered the system unsuitable
for the intended telecommunications application. Physical insight from the model
also helped to develop a new simple and effective modified SVM with feedforward dutycycle compensation scheme that reliably minimizes current
distortion and voltage ripple while keeping the same single dimension control.
8
2.
MATHEMATICAL DESCRIPTION OF SWITCHING
POWER CONVERTERS AND THEIR LARGE AND
SMALLSIGNAL MODELING
This chapter starts with a review of statespace descriptions for PWM converters
in continuous and discrete time forms followed by an outline of smallsignal model
derivation in both time forms. Afterwards variations of the method of generalized
averaging are introduced. In addition the approaches to synthesize averaged circuit model
for PWM converters are also discussed and a comparison analysis of these methods is
presented. Then a new modeling procedure to obtain autonomous averaged circuits of
PWM converters is outlined and illustrated through its application to the buck converter.
The resulting averaged circuit covers a wide range of operation, i.e. DCMCCM.
2.1
Characteristics and StateSpace Description of PWM Converters
The PWM converters considered in this work consist of linear resistive and
reactive elements, piecewise linear switching elements with the externally controlled
ones activated at a constant frequency, and input and output power terminals that can
exhibit ac or dc variables as depicted in Fig. 2.1.
2.1.1. Continuoustime statespace equations
The conditions imposed upon the elements of the power stage allow the
converters to be described, in between certain switching instants tk,i, by linear timeinvariant ordinary differential equations of the form [V4]
d x(t) = A ⋅ x(t) + B ⋅ u( t )
k ,i
k ,i
dt
t k ,i −1 < t ≤ t k ,i ,
(2.1)
where state vector x(t) is n x 1, state transition matrix Ak,i is n x n, input matrix Bk.i is
n x r and input vector u(t) is r x 1.
Switching instants tk,i are determined by combinations of control parameters
and/or state variables from the power stage and control circuitry. Subscript k corresponds
to switching cycle, whose duration is assumed constant and designated by Ts, and
subscript i corresponds to a time interval within each cycle during which the system
maintains the same switch configuration, Fig. 2.3. Entries for matrices Ak,i and Bk.i
depend upon switch conditions (on or off), which determine circuit structure in between
switching instants, and component values. The combinations that determine the switching
instants in the kth cycle can be described by the set on m constraints
c( x(t k ), p(t k ), u( t k )) = 0 ,
where p(tk) is a q x 1 vector of independent controlling parameters.
9
(2.2)
POWER STAGE
SOURCE
LOAD
(DC/AC)
(DC/AC)
CONTROL
Fig. 2.1. PWM converter structure.
10
2.1.2. Sampledata statespace equations
In general the change on the converter statespace vector x(t) over one switching
cycle, i.e. from tk to tk+1, can be expressed by the n sampleddata relations
x(t k +1 ) = f ( x(t k ), p(t k ), u( t k )) ,
(2.3)
upon integration of (2.1). f ( . , . , . ) represents a vector valued nonlinear function that in
our case can be simplified to [V3, V4]
x(t k +1 ) = F ( p(t k ) ) ⋅ x(t k ) + H ( p(t k ), u( t k )) ,
(2.4)
where F (.) and H (.) are n x n and n x 1 matrices respectively that involve matrix
exponentials of Ak,i and are easily computable in terms of Ak,i, Bk,i and u(t).
When a dcdc PWM converter is operating in steady state the state space vector
returns at the end of the switching cycle to the same value it had at the beginning of it, i.e.
x(t k +1 ) = x(t k ) = F ( p(t k ) ) ⋅ x(t k ) + H ( p(t k ), u( t k )) = X
(2.5)
is a constant as well as p(tk)=P and u(tk)=U. As a result (2.2) and (2.5) become
c( X , P ,U ) = 0
(2.6)
X = F ( P ) ⋅ X + H ( P ,U ) .
(2.7)
and
Smallsignal dynamics of perturbations around an orbit can now be obtained by
keeping up to linear terms of the Taylor series expansion of equations (2.6) and (2.7), i.e.
∆x(t k +1 ) = F ( P + ∆p(t k ) ) ⋅ ( X + ∆x(t k ) ) + H ( P + ∆p(t k ),
U + ∆u(t k ) ) − X
(2.8)
and
c( X + ∆x(tk ), P + ∆p(tk ),U + ∆u(tk ) ) = 0 ,
where ∆x and ∆p represent those perturbations.
After carrying out some cancellations on the series expansions one obtains:
11
(2.9)
∆x(t k +1 ) = F ( P ) ⋅ ∆x(t k ) + ∂ F ( P ) ⋅ ∆p(t k ) ⋅ X
∂p
+ ∂ H ( P ,U ) ⋅ ∆p(t k ) + ∂ H ( P ,U ) ⋅ ∆u(t k )
∂p
∂u
(2.10)
and
∂ c( X , P ,U ) ⋅ ∆x(t ) + ∂ c( X , P ,U ) ⋅ ∆p(t )
k
k
∂p
∂x
+ ∂ c( X , P ,U ) ⋅ ∆u(tk ) = 0.
∂u
(2.11)
which are basically a discrete smallsignal model in implicit form and almost always
needs to be solved numerically to compute the desired discrete transfer functions. Their
continuoustime counterparts can then be computed numerically.
2.1.3
Sampleddata modeling of a simple PWM converter
Since this modeling process gets very involved for highorder systems, some
simplifications based on practical converter characteristics are usually possible. To
illustrate this process, the largesignal sampleddata model for the simple buck PWM
converter, shown in Fig. 2.2, with the socalled peak current control and in CCM of
operation is developed. In this system, in CCM operation, there are two state variables,
inductor current and capacitor voltage, i.e.
x(t) = [i L vC ] ,
T
(2.12)
and the two switching configurations (circuit topologies), depicted in Fig. 2.3, i.e. interval
subscript i in (2.1) takes the values 1 and 2. These switching configurations are
determined by the conduction state of the switch, i.e. on or off, and give origin to matrices
Ak,i and Bk,i,
Ak ,1 = Ak ,2
−1 L
0
= A=
1 C 1 R ⋅ C
1 L
Bk ,1 = ,
0
and
12
T
,
(2.13)
(2.14)
0
Bk ,2 = .
0
(2.15)
The remaining term in (2.1), input vector at ime tk, is given by
u (tk ) = vi (tk ) .
(2.16)
Duration of the first interval in transient regime is determined from conditions
represented in Fig. 2.4 where inductor current waveform, modulating ramp and current
reference are shown. From Fig. 2.4 the switching constraint that determines dk (the duty
ratio for interval i=1) is calculated as
i* ( t k ) − mr ⋅ d k ⋅ Ts = iL ( t k ) + m1 ⋅ d k ⋅ Ts ,
(2.17)
*
where i ( tk ) represents inductor current reference (independent control parameter p(tk)
in (2.2)), iL ( tk ) is the inductor current values at time tk, mr and m1 correspond to
modulating ramp slope and approximated inductor current slope during interval 1
respectively when capacitor voltage is assumed constant over one switching cycle, i.e. Ts.
The large signal sampleddata model for the buck converter, after assumption of
constant control during each interval can be described as
x(t k + d k ⋅ Ts ) = F1(d k ) ⋅ x(t k ) + H 1(d k ) ⋅ u(t k )
(2.18)
x(t k + Ts ) = F2 ( d k ) ⋅ x(t k + d k ⋅ Ts ) + H 2 ( d k ) ⋅ u(t k + d k ⋅ Ts ) ,
(2.19)
and
where
F1 ( d k ) = e
A1⋅d k ⋅Ts
∫
d k ⋅Ts
, H 1( d k ) = o
e
A1 ⋅σ
⋅ B1 ⋅ dσ
(2.20)
and
F2 ( d k ) = e
A2 ⋅( 1−d k )⋅Ts
,
H 2 ( dk ) = ∫
13
( 1− d k )⋅Ts
o
e
A2 ⋅σ
⋅ B2 ⋅ dσ .
(2.21)
S
L
vi
C
R
iL
Gate
i ∗Ref
∑
vG
Comp
Ramp
Fig. 2.2 Simple buck PWM converter with current feedback.
14
15
Vi
C
Interval i=1
D
L
R
Vi
Interval i=2
C
L
R
t k + d k TS < t < t k +1
D
S
OFFstate
Fig.2.3. Buck converter circuit topologies
t k < t < tk + d k TS
S
ONstate
VG
Interval i=1
Interval i=2
On
Off
i*
On
mr
iL
m1
Interval i=1
Interval i=2
Off
ramp
m2
iS
vD
t
vC
tk
tk+dk.Ts tk+1
tk+1+dk+1.Ts
TS
Fig. 2.4 Relevant waveforms for dutycycle calculation
16
Concatenation of (2.28) and (2.19) provides a cycletocycle representation of the system
that can describe the behavior either at the beginning of the cycles, (2.22), or at the
switching instants, (2.23).
x (tk + 1 ) = F2 ( d k ) ⋅ F1( d k ) ⋅ x(tk ) + ( F2 ( d k ) ⋅ H 1( d k ) +
H 2 ( d k )) ⋅ u(tk ).
x (tk + 1 + d k ⋅ Ts ) = F1( d k ) ⋅ F2 ( d k ) ⋅ x(tk + d k ⋅ Ts ) +
( F2 ( d k ) ⋅ H 1( d k ) + H 2 ( d k )) ⋅ u(tk + d k ⋅ Ts ).
(2.22)
(2.23)
When control signals vary slowly as compared to switching period, the matrix
exponentials can be approximated by keeping up to the linear terms in their series
expansion. That is,
Fi = e
Ai ⋅σ
≈ I + Ai ⋅ σ ,
(2.24)
and
F j Fi = e
A j ⋅σ A ⋅λ
i
e
≈ I + A j ⋅ σ + Ai ⋅ λ ,
(2.25)
which are the same approximations made in the continuoustime statespace averaged
method.
After using these approximations in (2.22) the largesignal model becomes
x (t k +1 ) = Φ( d k ) ⋅ x(t k ) + Ψ ( d k ) ⋅ u(t k )
(2.26)
where
Φ (d k ) = I + A1 ⋅ d k ⋅ TS + A2 ⋅ (1 − d k ⋅ TS ) = I + A ⋅ TS
17
(2.27)
and
Ψ (d k ) = ( I + A ⋅ TS ) ⋅ B1 ⋅ d k ⋅ TS .
(2.28)
Linearization of (2.26), leads to an approximate discrete smallsignal model of the
following form
∆ x (tk +1 ) = Φ( d k ) ⋅ ∆ x(tk ) + ( I + A ⋅ TS ) ⋅ B1 ⋅ TS ⋅ u( tk ) ⋅ ∆ d k +
Ψ ( d k ) ⋅ ∆ u(tk ).
(2.27)
Similarly linearization of (2.17) provides ∆ d k as
∆ d k = −∆ iL ( tk ) /( m1 + mr ) ⋅ Ts + ∆ i* ( tk ) /( m1 + mr ) ⋅ Ts ,
(2.28)
which when substituted in (2.27) gives after some manipulations the final form
∆ x (tk + 1 ) = Κ ⋅ ∆ x(tk ) + Λ ⋅ ∆ i* ( tk ) + Μ ⋅ ∆ vin(tk ) .
(2.29)
Equations 2.12 through 2.27 show that large and smallsignal sampleddata model
can be easily and systematically obtained for simple PWM converters in open and closed
loop operation. Unfortunately modeling of interconnected converters from their
independent models is not a straightforward procedure and most of the time requires a
complete new derivation.
2.2. Generalized Method of Averaging for PWM Converters
The main objective for applying the generalized method of averaging, also known
as KBM (Krilov, Bogoliubov, Mitropolski), to time varying systems, such as PWM
converters, is to obtain an autonomous model that closely describes a moving average of
the variables in the original system. In other words, we are trying to derive a simpler
model that retains some of the main properties, a slow dynamics manifold, of the initial
system.
18
In this chapter a general description of this method following the lines in [K5] and
how to apply it to a simple PWM converter in CCM are presented. A simple way to
estimate information about ripple of the variables is also discussed.
2.2.1. Procedures of the method
In order to apply the KBM method to a system it is necessary to cast it in the
standard form
d
x( t ) = ε ⋅ F ( t , x ),
dt
x( t 0 ) = x 0 ,
(2.30)
where ε is a small nondimensional parameter and F is a vector valued function (see K5
and the references within for a rigorous justification of averaging for (2.30)). The
integral
1 T
F ( s ,⋅ )ds ,
T →∞ T ∫ 0
G( ⋅ ) = lim
(2.32)
is defined as the time average of (2.30) and leads to the new timeinvariant averaged
model
y (t ) = ε ⋅ G( y ),
y( t0 ) = y0 .
(2.33)
When the system is periodic or quasiperiodic, as in PWM converters, the integral
in (2.32) is finite and hence the limit exists.
The KBM method is based on the change of variables
x (t ) = y( t ) + ε ⋅ ψ 1 ( t , y ) + ε 2 ⋅ ψ 2 ( t , y ) + ε 2 ⋅ ψ 3 ( t , y ) + ... ,
(2.34)
where ψ i are functions of time with zeroaverage value, which transforms the original
system, i.e (2.30), into the time invariant system
19
d
y (t ) = ε ⋅ G1 ( y ) + ε 2 ⋅ G 2 ( y ) + ε 3 ⋅ G3 ( y ) + ... .
dt
(2.35)
In order to obtain a set of equations in the new variable y, (2.30), (2.34) and (2.35)
need be used. First, (2.34) gets differentiated with respect to time, then (2.30) is used to
eliminate x& , (2.35) to eliminate y& , and (2.34) to eliminate x. Then terms with the same
power of ε are equated to get a system of equations that can be sequentially solved for
ψ i ( t , y ) and G i ( t , y ) .
2.2.2. Illustration of the generalized method of averaging for a simple PWM
converter
This process is presented here for single switch PWM converters in CCM operation, i.e.
two intervals per switching cycle. In the next section the same process will be specifically
used with the open loop buck converter.
Equation 2.30 can be written as
d x(t) = [ A + h( t ,T ) ⋅ ( A − A )] ⋅ x(t)
2
s
1
2
dt
+ [ B 2 + h( t ,Ts ) ⋅ ( B1 − B2 )] ⋅ u( t )
(2.36)
where matrices Ai and Bi correspond to those defined in (2.1) for intervals 1 and 2 after
dropping the index k, and
h( t ,Ts ) = H [ d ( t ) − ramp ( t ,Ts )] .
(2.37)
where H(z) is the Heaviside or unit step function, d(t) is the dutycycle control signal and
the function ramp(t,TS) corresponds to the PWM modulating signal. The latter is
described by using the module operation
ramp ( t ,Ts ) =
t mod( Ts )
.
Ts
(2.38)
Calculation of the parameter ε is performed by selecting the largest absolute
value of the entries in matrices Ai and Bi, designated by ξ in (2.39), and multiplying it
by Ts, i.e.
20
ε = max
i,j
{
ai , j , bi , j
}⋅ T
s
= ξ ⋅ Ts .
(2.39)
If time is scaled as
t = Ts ⋅ τ ,
(2.40)
equations (2.36) and (2.37) can be expressed in terms of ε and τ as
d x(τ) = ε ⋅ { [ 1 ⋅ A + h( τ ,1 ) ⋅ ( A − A )] ⋅ x( τ)
1
2
dτ
ξ
ξ 2
1
h( τ ,1 )
+ [ ⋅ B2 +
⋅ ( B1 − B2 )] ⋅ u( τ )}
ξ
(2.41)
ξ
and
h( τ ,1 ) = H [ d ( τ ) − ramp ( τ ,1 )]
(2.42)
respectively. Thus application of the averaging operator (2.32) to the right hand side
(RHS) of (2.41) produces
G(y) = [
1
ξ
⋅ A2 +
+
d
ξ
1
ξ
⋅ ( A1 − A2 )] ⋅ y
⋅ [ B2 +
d
ξ
⋅ ( B1 − B2 )] ⋅ U ,
(2.43)
where d is the average dutycycle. The average model, after returning to the original time
scale, is given by
d
y( t) = [ A2 + d ⋅ ( A1 − A1 )] ⋅ y( t )
dt
+ [ B 2 + d ⋅ ( B1 − B2 )] ⋅ U ,
(2.44)
which is the same result obtained through statespace averaging. Estimates of variables
ripple can now be computed by continuing with the KBM method. Manipulation of
(2.34), (2.35) and (2.43) leads to
21
1
h( τ )
⋅ ( A1 − A2 ) ⋅ [ y + ε ⋅ ψ 1 + ε 2 ⋅ ψ 2 + ...]
ε ⋅ ⋅ A2 +
ξ
ξ
1
h( τ )
+ ε ⋅ ⋅ B2 +
⋅ (B1 − B2 )
ξ
ξ
= ε ⋅ G1 + ε 2 ⋅ G 2 + ε 3 ⋅ G3 + ...
(
)
∂ψ 1
∂ψ
+ε ⋅ 1 +
⋅ ε ⋅ G1 + ε 2 ⋅ G 2 + ...
∂τ
∂τ
∂ψ 2
∂ψ
+ε2 ⋅ 2 +
⋅ ε ⋅ G1 + ε 2 ⋅ G 2 + ... ... ,
∂τ
∂τ
(
)
(
(2.45)
)
from where equating terms with the same power of ε gives
ε:
ε2 :
ε2 :
1
1
h( τ )
h( τ )
(
)
(
)
A
A
A
y
B
B
B
⋅
+
⋅
−
⋅
+
⋅
+
⋅
−
2
1
2
2
1
2
ξ
ξ
ξ
ξ
∂ψ 1
,
= G1 +
∂τ
(2.46)
1
∂ψ 2
∂ψ 1
h( τ )
(
)
A
A
A
ψ
G
G
⋅
+
⋅
=
+
⋅
+
⋅
−
,
1
2
1
2
2
1
ξ
ξ
∂τ
∂τ
(2.47)
1
∂ψ 3
∂ψ 1
∂ψ 2
h( τ )
ξ ⋅ A1 + ξ ⋅ ( A1 − A2 ) ⋅ ψ 2 = G3 + ∂τ ⋅ G 2 + ∂τ ⋅ G1 + ∂τ .(2.48)
Equation (2.46) is used to solve for G1 by taking the average over one period with respect
to τ and the result is the same as the RHS of (2.44). Now G1 is substituted in (2.46) and
then the constant of integration is selected to make ψ 1 zeroaverage and of period Ts.
Similarly the other functions can be calculated to obtain a higher order approximation for
variables ripple (see [K5] for modeling of the boost converter and its ripple estimation).
22
2.2.3. Generalized method of averaging for the open loop buck converter
The converter in Fig.2.3 is considered here but in open loop and its continuoustime statespace equations, i.e. (2.36), after substituting (2.13)(2.15) reduces to
d x(t) = A ⋅ x(t) + h( t ,T ) ⋅ B ⋅ v ( t ) ,
1
s
1
in
dt
(2.49)
and
h( t ,Ts ) = H [ d − ramp ( t ,Ts )] .
(2.50)
The average equation is then given by
d y(t) = A ⋅ y(t) + d ⋅ B ⋅ v ( t )
1
1
in
dt
(2.51)
and (2.45) reduces to
1
ξ
⋅ A1 ⋅ y +
h( τ )
ξ
⋅ B1 = G1 +
∂ψ 1
,
∂τ
(2.52)
from where after some manipulations ψ 1 is obtained as
ψ1 (τ ) =
(
)
1
⋅ B1 [h( τ ) − d ]⋅ ramp (t ,1) + [1 − h( τ )]⋅ d + ⋅ d 2 − d (2.47)
ξ
2
1
and the remaining Gi for i=2, 3, … are zero.
23
2.3. Averaging Method for TwoTime Scale PWM Converters
Most PWM converters can be classified as one or twotime scale systems. A
method for the latter, developed very similarly by different authors [N2, S13, W3], is
presented here. The former are already covered by the method in section 2.2.
2.3.1. Statespace description for twotime scale PWM converters
The twotime scale characteristics of a PWM converter can be explicitly shown
by representing the system in the form
d
x (t ) = ε ⋅ f ( t , x , y ),
dt
x( t 0 ) = x 0 ,
(2.48)
d
y (t ) = g( t , x , y ),
dt
y( t 0 ) = y 0 ,
(2.49)
where ε is again a small nondimensional parameter, x and y are state vectors of
dimension n and m respectively, and f and g are vector valued functions.
The average model for (2.48) is defined as
d
X (t ) = ε ⋅ f 0 ( X ),
dt
X ( t 0 ) = x0 ,
(2.50)
with
1
Ts → ∞ T
s
f 0 ( x ) = lim
t +Ts
∫t
f (τ , x , φ(τ , x , t ′, y0 )) dτ ,
t ≥ t0 ,
(2.51)
where φ(τ , x , t ′, y0 ) is the solution of (2.49) with initial value y (t ′) = y0 and fixed x.
24
When x is fixed switch patterns in PWM converters do not change, and hence, if
φ(τ , x , t ′, y0 ) converges to a periodic function ψ (τ , x ) in a finite time (2.51) can be
simplified to
f0 ( x ) =
1
Ts
Ts
∫ 0 f (τ , x ,ψ (τ , x )) dτ ,
(2.52)
whose value is finite as described in section 2.2. Thus ψ (τ , X ) becomes the steadystate
solution of y (t) for fixed X.
For PWM converters (2.48) and (2.49) can be written as
dx
= Aisx ⋅ x + Aisy ⋅ y + Bis ⋅ u ,
dt
(2.53)
dy
= Ai fx ⋅ x + Ai fy ⋅ y + Bi f ⋅ u ,
dt
(2.54)
where superscripts s and f stand for slow and fast in Ai and Bi matrices, which are
constant during interval i.
2.3.2. Practical procedure for the method
Starting with the PWM converter equations in the form of (2.53) and (2.54) the
following steps summarize the averaging procedure.
1.
Assume slow variables x as fixed in the equations for fast variables y, (2.54):
{
}
dy
= Ai fy ⋅ y + Ai fx ⋅ X + Bi f ⋅ u .
dt
25
(2.55)
2.
Compute steadystate solution yss of fast variables in (2.55);
3.
Substitute yss into (2.53) to get
dx
= Aisx ⋅ x + Aisy ⋅ y ss + Bis ⋅ u .
dt
3.
(2.57)
Compute the average of (2.57), over one switching period,
f0 ( x ) =
1
Ts
r
t k ,i
∑∫t
i =1
k ,i −1
{A
sx
i
}
⋅ x + Aisy ⋅ y ss + Bis ⋅ u dt ,
(2.58)
to obtain the average model
dX
= f0 ( X ) .
dt
2.4.
(2.59)
Synthesis Method for Averaged Circuit Models of PWM Converters
Development of autonomous averaged and smallsignal circuit models according
to [S4, V8] is presented in this section. Their intent is to reproduce statespace averaging
results for single switch PWM converters. In [S4], an inplace circuit averaging is
performed and analytical support is given whereas in [V8] an equivalent 3terminal
circuit is sought for the socalled PWM switch.
2.4.1. Inplace averaging
When the moving average operation over one switching cycle given by
26
y( t ) =
1
TS
t
∫t −T y(σ ) dσ
(2.60)
S
is applied, inplace to each branch variable of PWM converters, in steady state operation,
the transformed branch variables satisfy the same node and mesh constraints as the
original variables. Therefore the synthesis of an averaged circuit model can be oriented
towards a circuit layout topologically equivalent to the original simple PWM converter.
Since a requirement for linear reactive elements not to be altered by the moving average
operator is that the latter and differentiation with respect to time commute, i.e.
d
[ y( t )] = d 1
dt
dt Ts
1
∫ t −Ts y(σ ) dσ = T [y(t ) − y(t − T )]
t
s
s
(2.61)
=
1
Ts
d
d
∫ t −Ts dσ y(σ ) dσ = dt y( t ) ,
t
which implies continuous differentiability for the state variables, i.e. their first time
derivative to be continuous. Unfortunately this is not the case for the PWM converters
treated here as stated by (2.1) and hence the moving average of the state variables do no
satisfy the converter’s state equations in general.
Application of the one cycle moving average operator in (2.60) to the statespace
representation of the PWM converter in (2.1), and reproduced here for clarity,
d x(t) = A ⋅ x(t) + B ⋅ u( t )
k ,i
k ,i
dt
t k ,i −1 < t ≤ t k ,i ,
(2.62)
leads to the form
d x(t) =
dt
1 t
[Ak ,i ⋅ x(s) + Bk ,i ⋅ u( s )]⋅[H ( s − t k ,i−1 ) − H ( s − t k ,i )] ds ,
Ts ∫ t −Ts
27
(2.63)
which is valid for all k,i since H( .), the Heaviside step function, in the last bracket selects
the appropriate time intervals for matrices Ak,i and Bk.i.
Direct computation of this moving average would require keeping track of
intervals within each switching cycle, which is a terrible burden. Instead an approximated
average per switching cycle described by
d X(t) =
dt
1
Ts
∫ t −T [A
tk
k
s
k ,i ⋅ x(s) + Bk ,i ⋅ u( s )]⋅[H ( s − t k ,i − 1 ) − H ( s − t k ,i )] ds
(2.64)
is used, where X is the new averaged state and tk =t. In other words the moving average
interval of width Ts and the switching cycle are assumed to coincide.
[S4] provides a theorem regarding the synthesis of an averaged circuit for a PWM
converter with a single controlled and linear time invariant components. The converter
must fulfill the following conditions:
(a)
be partitioned as shown in Fig. 2.5,
(b)
have unique solutions for voltage and currents of its branches, e.g. no
capacitorvoltage source loop, etc.,
(c)
have a hybrid representation for the RESISTORS multiport in Fig. 2.5 with
controlling port variables taken as currents for those ports connected to
current source or inductive ports and as voltage for those ports connected
to voltage source or capacitive ports, with a single currentcontrolled
switch port and a single voltage controlled switch port.
Given all this it is possible to obtain an averaged circuit model by replacing the
twoport switch network with a resistive twoport whose hybrid representation is
H S (d ) =
d
⋅ H 22 ,
1− d
(2.65)
for d ≠ 1 , where H22 is the hybrid immittance seen by the switch twoport when all
current source and inductive branches are replaced by open circuits and all voltage source
and capacitor branches are replaced by short circuits.
28
Since application of this theorem is restricted to single switch converters, a
procedure introduced in [V8] for the PWMswitch and then complemented in [L11, X4,
Y2], which also leads, in a more direct way, to the synthesis of a valid circuit for the
same hybrid representation is shown instead.
2.4.2. PWMswitch equivalent circuits
This method was proposed in [V8] for dc and smallsignal model. It starts by
noting that simple PWM converters include one active switch (externally controlled
device) and one passive switch (diode). The combination of these two switches, shown in
Fig. 2.6(a), is the socalled PWM switch. Because at most one switch is conducting at a
time, some relationships for the instantaneous terminal variables of the PWM switch,
depicted in Figs. 2.6(b) remain invariant in simple PWM converters, i.e.
i ( t ) ; 0 ≤ t ≤ d ⋅ Ts
ia ( t ) = c
0 ; d ⋅ Ts ≤ t ≤ Ts
(2.66)
v ( t ) ; 0 ≤ t ≤ d ⋅ Ts
vcp ( t ) = ap
,
0 ; d ⋅ Ts ≤ t ≤ Ts
(2.67)
and
where i and v represent instantaneous port variables, subscripts a, p, c stand for active,
passive and common respectively, and d.Ts represents the interval within the switching
cycle when the active switch is on. From here an average model for the PWM switch,
valid in steadystate operation, i.e. fixed dutyratio, is developed by computing, from the
waveforms in Fig. 2.6(b), average current and average voltage at its terminals. That is,
Ia = d ⋅ Ic
(2.68)
and
Vcp = d ⋅ ( Vap − I c ⋅ req ⋅ ( 1 − d )) ,
(2.69)
where I, V and d represent average quantities and req is the equivalent resistor that causes
the jump in vap . That equivalent resistor is usually a combination of capacitor equivalent
series resistor (esr) and/or load resistor. For instance in the boost and buckboost
converters re is the parallel combination of output filter capacitor’s esr and load resistor.
29
An equivalent circuits for the average model of the PWM switch, i.e. (2.68) and
(2.69), is shown in Fig. 2.7. [V8] uses an ideal transformer instead of the controlled
sources. Note that the circuit representation for the PWM switch is not unique but must
have the same terminal variables relations. The smallsignal model of the PWM switch
can be obtained by linearizing equations (2.68) and (2.69). The final result [V8] is
∆ ia = d ⋅ ∆ ic + I c ⋅ ∆ d ,
∆ vap =
∆ vap
d
+ ∆ ic ⋅ req ⋅ ( 1 − d ) − [ Vap + I c ⋅ ( 2 ⋅ d − 1 ) ⋅ req ] ⋅
(2.69)
∆d
d
.
(2.70)
Computation of typical transfer functions such as control or input voltage to either
state variables or output voltage can be carried out by placing the smallsignal PWM
model into the converter and then using node and mesh equations.
DCM of operation is covered in [V8] for the same type of analysis. Similar works
in [X4, Y2] cover DCM and CCM operation respectively. Instead of transformer and
equivalent resistor to replace the switchdiode pair the models exhibit a controlled current
source and a controlled voltage source. The latter represents average switch current
whereas the former represents average diode voltage. In [L11] a simplified version of
[Y2], no capacitor esr included, is used to model simple PWM converters with a current
feedback loop.
2.5.
Analysis of Strengths and Weaknesses of these Methods
Of all these methods for switching power converters generalized averaging
(KBM) is the most systematic, can include any type of feedback loops but provides very
little physical insight and becomes almost untraceable for high order systems. Even
though state variables’ ripple can be approximated to an arbitrary degree it requires
keeping track of phase relationships between PWM modulating signal perturbations in
control and input signals. In other words time varying effects must be considered, which
conflicts with the main purpose of averaging, i.e. obtaining an autonomous
representation.
Physical insight is incorporated into twotime scale averaging for switching power
converters with the classification of fast/slow state variables based on waveforms
analysis. Moreover the procedure for this method of averaging is systematic and can
handle PWM as well as several resonant converter types. Unfortunately energy holding
30
i
0
REACTIVES
RESISTORS
1
v
SWITCH
SOURCES
Fig. 2.5. Partition of PWM converter structure.
31
voltage port
32
d
p
1d
c
0
vap(t )
Vap
0
Ia
ia(t )
Fig.2.6. The PWM switch
vcp( t )
ic (t )
a) Structure and terminal variables
vap(t )
a
ia (t )
current port
current port
d Ts
Ts
0
Vcp
vcp(t )
0
ic(t )
d Ts
a) Terminal waveforms
Vap − IC req (1−d)
Ic
Ts
(1 − d) ⋅ d ⋅ re
a
c
ia ( t )
ic ( t )
d ⋅ v ap ( t )
d ⋅ ic (t)
p
Fig. 2.7.PWMswitch equivalent average circuit.
33
elements, dealt with in more detail in Chapter 4, are not allowed within the fast state
variables and steadystate conditions are used in some portions of the procedure. These
steadystate conditions lead to unaccounted dynamic characteristics, g.e. input, control
and ripple induced effects, which constrain model ranges, g.e. order, bandwidth.
PWM switch models and their extensions to some types of resonant converters
give very good physical insight and allow for straightforward dc and ac calculations
through circuit analysis tools. However, constraints imposed on the switchdiode pair
configuration limit the set of converters that can be modeled.
Inplace circuit averaging preserves converter structure and hence provides strong
physical insight. In addition a systematic and rigorous procedure leads to analytical
hybrid representation for the switchdiode pair. Regrettably, this procedure can become
very involved for high order systems and deals with CCM and DCM separately as it is
also the case for all previous methods. Even though PWM switch modeling and its
extensions deal with multiple switches in a systematic way there is no provision for fullbridge based converters or energy storage elements.
2.6.
A New Procedure for Averaged Circuit Models
Strong features from some of the methods discussed above are complemented
with analog simulation and series expansion practices as well as heuristic guidelines to
form a new modeling procedure. A simplified version of the socalled duomode average
model [R5] that covers DCM and CCM for the buck converter with current feedback loop
is developed to illustrate the new procedure and then simulation results from switching
and average models are presented.
2.6.1. Philosophy of the new average modeling procedure
Representation of port characteristics, e.g. impedances, average variables, as well
as transfer characteristics, e.g. voltage conversion ratio, will be the major property sought
for the average circuit model.
The starting point for the procedure is the set of openloop typical waveforms in
transient regime and of switching structures through which the converter passes, Fig. 2.8.
Inclusion of transient regime conditions overcomes limitations induced by steadystate
conditions used in PWMswitch modeling and in twotime scale averaging methods.
Then classification of state variables into fast and slow types from the twotime scale
method is used together with circuit topologies and typical waveforms to select, at input
and output ports, filtering networks (slow state variable components) whose structures do
not get altered by switch transitions, i.e. linear time invariant (LTI) networks, so that their
contributions to openloop input/output characteristics (impedances, dynamics) are
preserved.
34
To keep consistency with this goal the equivalent driving and/or loading
controlled sources for those LTI filtering networks must be identified and their moving
average should be efficiently and accurately approximated (for this task onecycle
average has been heuristically selected). In other words we are trying to mimic the
moving average properties stated in (2.61), from inplace averaging section, by applying
the onecycle average of those controlled sources to the LTI networks in the previous
paragraph.
At this stage feedback loop effects, e.g. algebraic and dynamic constraints, can be
incorporated for stability and transient analysis, and finally a simulator specific
implementation should be developed.
In order to help with application of the procedure it gets described in a stepbystep fashion together with guidelines in the next section.
2.6.2. Steps of the new average modeling procedure and their guidelines
Step 1: Classify state variables according to slow/fast dynamics with respect to switching
frequency and select meaningful slow states for average circuit model. These states
should have neither zero steadystate average nor a zero value during a significant
amount of time within the switching cycle and their moving average main frequency
components should be much lower than the switching frequency, Fig. 2.9.
Step 2: Select linear time invariant (LTI) input and output parts, i.e. subnetworks made
of sources and passive components whose structures do not get altered by switch and
diode transitions, Fig. 2.10.
Step 3: Identify “dependent” variable(s) drawn from input network(s) and “independent”
variable(s) delivered to output network(s), all from the Step 2, to be represented as
controlled sources. These variables should not create discontinuities in state variables
regardless of initial conditions, i.e. no current sources in series with inductors or voltage
sources in parallel with capacitors, Fig. 2.11.
Step 4: Derive expression for onecycle average of controlled sources in Step 4 from
typical waveforms and circuit topologies. In most cases a few low order terms of power
series approximation for waveform description will suffice, Fig. 2.12.
Step 5: Derive algebraic constraints in transient regime, e.g. variablestate dependent
switching instants, DCMCCM boundary conditions; as a function of input, control and
fast dynamics variables. The latter should not be related to an energy holding component,
described in detail in Chapter 4, since its state variable contributes with a dynamic
constraint, i.e. an additional state, which usually requires a particular treatment. Here also
low order terms in power series approximation of waveforms may suffice, Fig. 2.13.
Step 6: Incorporate feedbackloop induced algebraic constraints and additional estates
(e.g. control and state dependent switching instants, compensator own states). By starting
35
with an open loop system and later including feedback loops effects it is very likely that
only this step will need modifications when changing control strategies, Fig. 2.14.
Step 7: Use common and reliable analog simulation practices to implement the average
model in circuit simulators and to blend models for different operating modes (e.g.
closing a loop around an operational amplifier to find zeros or the inverse of a function,
manipulating equations to avoid undefined operations such a division by zero, detecting
inadmissible variable values such as bipolar output from a rectifier, on the fly state
variables removal/addition etc.), Fig. 2.15.
2.6.3. Application of the new procedure to the buck converter
Figures 2.2, 2.3 and 2.4 show the buck converter with current feedback loop, its
circuit topologies and its typical waveforms respectively in CCM. Fig. 2.16(a) exhibits an
averaged circuit model for the same converter, which can be derived by applying the new
procedure as detailed next
Classification of state variables in Step1, according to their dynamics speed,
labels inductor current iL and capacitor voltage vC, shown in Figs. 2.4 and 2.9, as slow
type. In Step 2 the voltage source gets easily identified as linear time invariant input
structure whereas the second order filter becomes the output side counterpart, Fig. 2.10.
Step 3 identifies switch current and diode voltage as “dependent” variable drawn
from LTI input part and “independent” variable delivered to LTI output part in the
previous step, Figs. 2.8 and 2.11.
In Step 4 the onecycle average both for switch current iS and diode voltage vD ,
in Figs. 2.8 and 2.12 are calculated as
iS = d ⋅ iL
(2.71)
vD = d ⋅ vin .
(2.72)
and
where d , iL and vi are dutyratio command, average filter inductor current and input
voltage respectively.
From Fig. 2.8 peak and average inductor current, i pk and iL are related up to a
first order approximation by
i pk = i L +
[
]
1
∆ iup ⋅ d + ∆ i dwn ⋅ (1 − d ) ,
2
36
(2.73)
where
(vi − vC )
∆ iup = m1 ⋅ d ⋅ Ts =
⋅ d ⋅ Ts ,
(2.74)
vc
⋅ ( 1 − d ) ⋅ Ts .
L
(2.75)
L
and
∆ idwn = m2 ⋅ (1 − d ) ⋅ Ts =
For later use d2 is defined as
d2 =
i pk
m2 ⋅ Ts
.
(2.76)
Algebraic constraint derived in Step 5 corresponds to CCMDCM boundary
condition, Fig. 2.1.3. Typical operating waveforms and circuit topologies for the buck
converter in DCM operation are shown in Fig. 2.17. Development details for the average
model in DCM shown in Fig. 2.18 will be presented after completing derivation in CCM .
Step 6 derives the algebraic constraint induced by current feedback loop
incorporation, Fig. 2.14, which determines switching time in terms of current reference
and state variables, i.e.
i* − mr ⋅ d ⋅ TS = i pk
(2.76)
Circuit simulator oriented implementation of average model in Step 7, includes
feedback loop around an operational amplifier to find the root (zero) of a function,
Fig. 2.15(a), as well as selection of a root within an admissible interval (dutycycle
between zero and one) and equation manipulation to avoid zero divisor condition,
Fig. 2.15(b).
Before applying the new modeling procedure to DCM operation a few
observations about the average circuit models for CCM in Fig. 2.16 are included. Even
though Model I is the only one derived so far, it can be transformed into the others
through wellknown controlledsource manipulation rules form circuit theory. As a result
all three models exhibit the same input, output and transfer characteristics, and obviously
any one can be transformed into the other two. Note that in Figs. 2.16(b) and (c) the
controlled sources represent in place average voltage or current for the switch or the
diode and are labeled as such.
The papers mentioned in the PWM switch model section replace switch and
diode by average controlled sources and they arrive to average circuit models II and III in
Fig. 2.16. From all of this it is clear that an inputoutput description of a switching power
converter may have multiple average circuit representations and that sometimes several
37
or even all of them can be generated by a single procedure. However our goal is to have a
modeling procedure that can handle as many types of PWM converters as possible, and
some resonant converters as a byproduct, without trying to derive multiple average model
structures for the same converter.
Figure 2.17 shows circuit topologies and typical waveforms for the buck
converter in DCM operation. The corresponding average model, presented in Fig. 2.18,
can be derived by following the new procedure.
Classification of variables according to their dynamics speed, Step 1, labels
capacitor voltage as the only slow variable since filter inductor current stays at zero
during a significant portion of the switching cycle. Therefore its onecycle average solely
depends on present switching cycle conditions, i.e. its own dynamic history does not
directly matter.
In Step 2 only output capacitor is selected as the LTI part in that side whereas the
voltage source gets selected for the input counterpart since the filter inductor is ruled out
because of the diode, which by being connected in series with it during the second
interval, prevents the current from becoming negative, i.e. makes the inductor look
nonlinear.
From Step 3 switch current and filter inductor current get respectively identified
as “dependent” variable drawn from the input LTI part and “independent” variable
delivered to the LTI output part.
Calculation of one–cycle average for the variables in Step3 is carried out in Step 4
with help from Fig. 2.17(b) where average switch current is clearly given by
iS =
i pk
2
⋅d ,
(2.77)
with
i pk = m1 ⋅ d ⋅ TS = m2 ⋅ d 2 ⋅ TS ,
(2.78)
where d 2 remains consistent with its definition in 2.76. Similarly onecycle average filter
inductor current is expressed as
iL =
i pk
2
⋅ (d + d 2 ) ,
which can be combined with 2.74, 2.75 and 2.78 to obtain
38
(2.79)
iL =
(vi − vC ) ⋅ d 2 ⋅ T
S
2⋅L
v
⋅ i .
vC
(2.80)
The latter is consistent with the claim that onecycle average filter inductor current is
completely determined by present cycle conditions and hence classifies as a fast variable.
The CCMDCM boundary condition, illustrated in Fig. 2.13, leads to the
expression
iL =
i pk
2
(2.81)
for which to check during the simulation when both average models, i.e. CCM and DCM
version, get combined below by following the approach called duomode model
presented in [R5] and shown in Fig. 2.19(a), which uses an ideal transformer
representation, to cover CCM and DCM operation. Fig. 2.19(b) shows the controlled
source equivalent version of the model. The transformer on the left with turns ratio 1:d
represents CCM operation whereas the other transformer, with turns ratio (d + d 2 ) : 1 ,
makes adjustments for DCM operation. Notice that if the constraint
d2 ≤ 1 − d
(2.82)
is enforced after calculating d2, according to (2.76), the turns ratio for the right
transformer reduces to 1:1 during CCM, which makes it irrelevant as far as inputoutput
transfer characteristics concerns and the correct model is seen. However during DCM
operation d2 must be adjusted to enforce (2.80), i.e. average inductor current. The analog
implementation diagram shown in Fig. 2.21 satisfies both CCM and DCM constraints.
Application of simple controlledsource manipulation practices from network
theory transforms the average circuits in Fig. 2.19 into those in Fig. 2.20 while keeping
the same inputoutput characteristics and all the relevant information avilable. The model
in Fig. 2.20(b) can be covered by the new procedure if the circuit simulation oriented
implementation in Step 7 is expanded to search for versatile analog circuit representations
that can change the number of state variables (filter inductor current state removed during
DCM) in real time during the simulation in a smooth and reliable fashion, i.e. no
convergence prone or discontinuity inducing structures.
Current feedback loop incorporation in Step 6 deals with (2.76) again but ipk is
now given by (2.78) instead of (2.73). This illustrates another situation with which the
versatile analog circuit representations in the previous paragraph must cope.
Regarding Step 7, Fig. 2.22 shows an analog circuit schematic to implement the
calculation, in real time during the simulation, of d and d2 to allow for smooth transitions
between CCM and DCM .
39
2.6.4. Model verification and comments
Verification of the average model was conducted through Saber simulations.
Schematics and template listings for these simulations are included in Appendix A.
Figure 2.23 shows duty ratios, inductor current and output voltage waveforms
from switch and average model. A zoomin on these waveforms is shown in Fig. 2.24. It
is apparent that average model waveforms very closely track those moving averages from
the switch model for large transients, both in CCM and DCM operation even when the
converter moves back and forth between those modes.
It is important to point out that there were no convergence problems for the
average model and that waveform tracking was very good for simulation step size more
than one order of magnitude larger than the step used with the switch model.
This close tracking indicates that the average model can be used to predict startup transients and feedback loops effects and hence it can help in power stage and control
design.
In these simulations good familiarity with the specific circuit simulator and
reliable simulation practices is a must.
40
41
vC
C
iS
iL
D
R
R
vD
C
i*
L
D
L
VG
S
S
dT S
m1
TS
mr
On
iL
ramp
Off
b) Operating waveforms
m2
Off
Fig.2.8. Starting point for new average modeling procedure
a) Switch structures (circuit topologies)
Vi
OFFstate
Vi
ONstate
On
t
42
TS
Fast
Variables
Slow
Variables
vC
TS
Fig.2.9. Step 1: Slow/fast variables separation
t
t
iL
t
t
Power
vi
ii
Loadx
LTI
Output
Part
LTI
Input
Part
Loadz
Converter
LF
vi
CF
RLoad
Fig. 2.10. Identification of Linear Time Invariant Input/Output parts.
43
44
ii
vi
ia
vb
Internal
Slow
States
Converter
iy
vx
vx
LF
LTI
Output
Part
CF
Loadz
Loadw
RLoad
Fig.2.11. Step 3: Identification of “dependent” variable drawn from input and
“independent” variable delivered to output LTI parts
vi
LTI
Input
Part
ia
Power
45
vD
iS
iL
*
VG
TS
vD
iS
Off
iL
On
vin
Off
t
b) Onecycle average
v D = d v in
iS = d iL
Fig.2.12. Step 4: Calculation of controlled source onecycle average
a) Dependent and independent waveforms
dT S
On
46
iLf
i*
VG
tk
ipk
TS
d2.Ts
m2
Off
tk+1
iL
t
2
(d 1 + d 2 )
i pk
=
2
i pk
b) Algebraic constraint derivation
iL =
m 1 d 1 TS = m 2 d 2 TS = i pk
Fig.2.13. Step 5: Calculation of algebraic constraints
a) Typical waveforms
d1.Ts
m1
On
47
iL
i*
VG
TS
mr
m2
Off
On
iL
ramp
Off
[
]
TS
2
2
m 1 d + m 2 (1 − d ) = i pk
2
b) Loopinduced constraint derivation
iL +
i * − m r d 1 TS = i pk
Fig.2.14. Step 6: Incorporation of feedback loop
a) Waveforms with feedback loop
dTS
m1
On
48
R
Y
+
_
OP
C
2 iL
d1 + d 2
1
Out
zero
zero
1d1
R
R
In
In
_
OP
+
C
_
OP
+
C
Root interval constraint
through limiter
d1
i * − m r d 1 Ts − i pk = 0
i pk (d 1 + d 2 ) − 2 i L = 0
d 2 m2 − d 1 m1 = 0
m1 d 1
m2
Out
b) Robust treatment of equation and root selection
Zero divisor
potential problem
i pk =
Z = [ i* , i L ,Vin ,Vo ]
Known input vector
d2 =
d2
Fig.2.15. Step 7: implementation of circuit simulator oriented average model
a) Root finder through loop
around operational amplifier
zero
f(X,Y) = 0
X
Zero divisor potential
problem
Root interval constraint
through limiter
49
Vi
vD
iLf
Lf
vD
Cf
Cf
Vi
iD
iLf
Lf
Cf
c) Averaged circuit model III
vS
RLoad
Fig.2.16. Average circuit model for buck converter in CCM operation
RLoad
a) Averaged circuit model I
iS
b) Averaged circuit model II
iS
Vi
iLf
Lf
RLoad
50
Vi
Vi
Vi
Cf
Cf
RLoad
RLoad
RLoad
vD
iS
iLf
i*
VG
TS
d2 TS
vC
m2
Off
iL
d) DCM operation waveforms
dT S
m1
mr
On
Fig.2.17. Buck converter in DCM operation
Cf
c) Idling interval
iLf=0
Lf
b) Diode conducting interval
iLf
Lf
a) Switch on interval
iLf
Lf
t
v in
ramp
Lf
Vi
iS
iL
Cf
RLoad
Fig. 2.18. .Average circuit model for buck converter in DCM.
51
52
vi
d
d+d2
1
iL
Cf
vx
iL
(d + d 2 )
Lf
RLoad
vx
(d + d 2 )
iL
b) Controlledsource based average circuit model
d vi
ix
a) Transformer based average circuit model
1
Cf
RLoad
Fig.2.19. Average circuit models for buck converter in CCM and DCM operation
d ix
Vi
Lf
53
d
iL
Cf
d
vi
d + d2
iL
b) Controlledsource based average circuit model
d
iL
d + d2
LF
a) Transformer based average circuit model
d + d2
CF
RLoad
RLoad
Fig.2.20. Input/output structure average circuit models for buck converter in CCM
and DCM operation
Vi
Vi
Lf
Limiter
Out
d2
1d
In
i pk
Eqn (2.73)
C
m2
Eqn (2.75)
d 2 ⋅ m2 ⋅ Ts − i pk = 0
zero
R
Eqn (2.79)
...
Y=
d
d
2
I
Lf
Vin
V
o
Fig. 2.21. Analog computation of d2.
54
_
OP
+
Limiter
Out
d2
1d
In
i pk
Eqn (2.73)
m2
Eqn (2.75)
d 2 ⋅ m2 ⋅ Ts − i pk = 0
C
zero
R
_
OP
+
...
Z=
*
i
d2
I
Lf
v
i
v
o
C
i * − mr ⋅ d ⋅ Ts − i pk = 0
zero
R
_
+OP
Out
d
1
In
Limiter
Fig. 2.22. Analog computation of d and d2 with feedback loop.
55
Fig. 2.23. Simulation results from average (reddashed) and switch (greensolid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage.
56
Fig. 2.24. Simulation results from average (reddashed) and switch (greensolid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage.
57
3.
MODELING OF THE ZVSFBPWM DCDC
CONVERTER
The new procedure for the derivation of autonomous average circuit models given
in the previous chapter is complemented here and then applied to the ZVSFBPWM
converter to get a new model. Previous averaged models were based on steadystate
operation and neglected variables’ ripple effects. As a result their range of validity, i.e.
frequency, large signal excursions, was limited and could not make a smooth transition
between CCM and DCM operation. Comparison of simulation results between new and
previous model shows that most of those limitations have been overcome. Furthermore a
smallsignal model is derived through linearization of the new average model and within
the circuit simulator; whereas previous small signal models were obtained through
graphical approximations of perturbations evolution.
3.1
ZVSFBPWM Converter Operation
The ZVSFB PWM dcdc converter and its typical switch structures (circuit
topologies) in CCM operation are shown in Fig. 3.1(a) and (b) whereas its typical
waveforms are depicted in Fig. 3.2. It operates with zerovoltage switching in both legs
and it is widely used in high power applications. Its complete analysis and design
considerations as well as its small signal models can be found in [S1] whereas some large
and smallsignal models are provided in [T4, V5].
3.1.1. CCM operation
Figure 3.1(b) and 3.2 describe CCM operation of the converter through equivalent
circuit structures for each major switch configuration interval, i.e. Charging, Transfer
and Circulating, whose characteristics are summarized below [S1, V5], and waveforms
for bridge voltage, Vab, blocking capacitor voltage, Vab, primary current, Ip, bus current,
Ibus, filter inductor current, If, rectifier’s output voltage, Vs, and output voltage, V0.
Blocking capacitor voltage is assumed negligible with respect to both input and reflected
output voltage as Fig. 3.2 suggests.
Charging Stage. Starts at t0 when input voltage Vin is applied between nodes a and
b, and ends at t1 when primary current equals reflected filter inductor current. On the
primary side, after neglecting transformer’s magnetizing current and second and higher
order terms in Taylor’s series expansion, input voltage determines the rate of change of
current in the leakage inductor LLk, i.e. m1 in Fig. 3.2 and given by
m1 =
Vin
,
Llk
58
(3.1)
while rectifier diodes short circuit transformer’s secondary winding and hence the output
voltage V0, whose changes over a switching cycle are assumed negligible, determines the
rate of change of current in the filter inductor Lf, i.e. m4 in Fig. 3.2 and given by
m4 =
V0
.
Lf
(3.2)
According to (3.1) the change in primary current during this stage is
approximately given by
V
I 1p − I 0p = in
Llk
⋅ (t1 − t0 ) = (m1) ⋅ (Dch ⋅ Ts ) ,
(3.3)
from where duty ratio for this stage, Dch, is given by
I 1p − I 0p
= Dch .
m1 ⋅ Ts
(3.4)
Similarly from (3.2) the change in the filter inductor current during this stage is
approximately given by
V
I 1f − I 0f = 0
L
f
⋅ (t1 − t0 ) = (m4 ) ⋅ (Dch ⋅ Ts ) .
(3.7)
Current changes in (3.3) and (3.7) are related by the transformer’s turns ratio N, i.e.
(
)
I1f − I 0f = N ⋅ I1p − I 0p .
(3.5)
Transfer Stage. Starts at t1 after primary current equals reflected filter inductor
current with transformer in normal operation and hence instantaneous primary current
and filter inductor current are related by the transformer’s turns ratio and ends at t2 when
Vab becomes zero. Reflection of input voltage and transformer’s leakage inductance to the
secondary side gives, for this stage, the equivalent circuit shown in Fig. 3.1. From here
the rate of change of primary current, m2 in Fig. 3.2, is given by
Vin − N ⋅ V0
= m2 ,
Llk + N 2 ⋅ L f
(3.6)
and from Fig. 3.2 the duty ratio for this stage is
Dtrf
I 1p − I 0p
= Don −
.
m1 ⋅ Ts
59
(3.7)
60

Vin+
Ibus
S2
S1
a
S4
b
N:1
a) Circuit schematic
Vcb Ip
+ 
Cb Llk
S3
If
Cf
_
RL Vo
+
Vin /N
2
Llk /N
I bus /N
Llk /N
I bus /N
2
2
Vs
Vs
Vs
If
Lf
If
Lf
If
Lf
RL
RL
V0
RL
Circulating
V0
Transfer
V0
Charging
b) Switch structures in CCM
I bus /N
Vin /N
Fig. 3.1. ZVSFB PWM converter

Vs
+
Lf
Vin /N
Llk /N
ab
S 2 , S3
Charging
Circulating
V
S2 , S4
Transfer
Charging
S1 , S4
V
in
Don⋅Ts
Dtrf ⋅Ts
VCb
m2
Ip
m1
I
m3
I 0p
If
I
f
0
m4
I bus
I 2p I p
3
p
1
I 2f
N ⋅ m2
N ⋅ m3
I 1f
If
I 3f
Vo
Vs
t0 t1
t2
t3
t
to +Ts
to
Fig. 3.2. Typical ZVSFB PWM converter waveforms in CCM.
61
Change in filter inductor current is given by
V / N −V
I 2f − I 1f = in 2 0
L / N +L
f
lk
⋅ (t2 − t1 ) = ( N ⋅ m2 ) ⋅ (Dtrf ⋅ Ts ),
where m2 is defined by the first bracket and Dtrf =
(3.8)
t 2 − t1
.
Ts
Circulating stage starts when bridge voltage Vab becomes zero, primary current
and filter inductor current are related by the transformer’s turns ration, and the change in
inductor current for this interval is expressed as
V0
I 3f − I 2f =
L / N2 + L
f
lk
⋅ (t3 − t2 ) = ( N ⋅ m3 ) ⋅ [(1 − Don ) ⋅ Ts ] ,
(3.9)
where m3 is defined by the first bracket, and the commanded dutyratio, Don, is given by
Don = Dch + Dtrf .
(3.10)
Equations (3.1) through (3.6) together with Fig. 3.3 can now be used to calculate
the onecycle average of filter inductor current If, i.e.
If =
(I
f
0
)
(
)
(
)
+ I 1f
I f + I 2f
I f + I 2f
⋅ (Don − Dtrf ) + 1
⋅ Dtrf + 1
⋅ (1 − Don ) .
2
2
2
(3.11)
The set (3.1) through (3.11) represents the algebraic constraint set needed to develop the
average circuit model.
3.1.2. DCM operation
Typical waveforms for DCM operation are shown in Fig. 3.4. Clearly there is no
charging stage and hence commanded duty cycle determines duration of transfer stage.
Peak filter inductor current is given by
V / N −V
I fpk = in 2 0
L /N +L
f
lk
⋅ (t1 − t0 ) = ( N ⋅ m2 ) ⋅ (Don ⋅ Ts )
(3.12)
V0
I fpk =
L / N2 + L
f
lk
⋅ (t2 − t1 ) = ( N ⋅ m3) ⋅ (D 2 ⋅ Ts ) .
(3.13)
and by
62
Onecycle average inductor current is calculated from (3.8) and (3.9) as
If =
I fpk ⋅ (Don + D 2 )
2
,
(3.14)
which gives the same DCMCCM boundary condition as in the buck converter, i.e.
I fpk
If =
2
.
(3.15)
Equating (3.12) and (3.13) gives
D2 =
Don ⋅ m2
m3
(3.16)
and its substitution together with (3.12) into (3.14) gives the algebraic constraint on onecycle average inductor current, i.e.
m2 ⋅ (Don ) ⋅ Ts
m2
If =
1 +
.
m3
2
2
(3.17)
The same as in the buck converter, this constraint indicates that onecycle average
filter inductor current is not an independent state.
3.2.
New Average Circuit Model for the ZVSFB Converter
Systematic application of the new procedure leads to the inputoutput structure
average model of the ZVSFB PWM dcdc converter shown in Fig. 3.4(a) as detailed
next.
3.2.1. Step 1: Fast/slow classification of state variables
From Figs. 3.1 and 3.2, filter inductor current and output capacitor voltage qualify
as slow variables in CCM to be used as states in the average circuit model. However in
DCM only the output capacitor remains as a slow state. Filter inductor current stays at
zero during a significant amount of time within a switching cycle, which leads to having
its onecycle average fully determined by present switching cycle condition and hence
being converted to a fast variable.
Primary current is not considered a relevant average state variable, even though it
corresponds to leakage inductor state variable, because its moving average is zero in
steady state operation and exhibits large components at one half the switching frequency
and higher harmonics during transient regime. In other words no new information would
63
be provided in steady state and time varying effects would have to be included in the
model.
3.2.2. Step 2: LTI input/output parts
Output filter and input voltage source get selected as LTI networks according to
circuit topologies in Fig. 3.1(b).
3.2.3. Step 3: “Independent” variable drawn from LTI input network and
“dependent” variable delivered to LTI output network
Average bus current is the “dependent variable” drawn from input voltage source
whereas secondary rectifier’s output voltage is the “independent variable” applied to the
output filter during CCM operation. On the other hand one cycle average inductor current
becomes the sought independent variable fed to the output section during DCM operation
the same as in the buck converter.
3.2.4. Step 4: Calculation of onecycle average for the variables in the previous step
CCM. According to Figs. 3.1(b), 3.2 and 3.4(c) rectifier voltage is equal to zero during
charging stage; it becomes a function of input source voltage and output capacitor
voltage, during transfer stage after neglecting blocking capacitor voltage, i.e.
Vin
L
⋅ L f + V0 ⋅ lk2
N ,
Vs = N
Llk
+ Lf
N2
t1 ≤ t ≤ t2 ,
(3.18)
and only a function of capacitor voltage during circulating stage given by
Llk
N2 ,
Vs =
Llk
+ Lf
N2
V0 ⋅
t 2 ≤ t ≤ t1 .
(3.19)
From (3.18), (319) and Fig. 3.2 the onecycle average rectifier voltage given to controlled
source V2 can be expressed as
Vin
L
L
⋅ L f + V0 ⋅ lk2
V0 ⋅ lk2
N ⋅D +
N ⋅ (1 − D ) .
V2 = Vs = N
trf
on
Llk
Llk
+
L
+
L
f
f
N2
N2
64
(3.20)
Transfer
Circulating
S 2 , S3
Idling
S2 , S4
Transfer
Vab
S1 , S4
V in
Don⋅Ts
D2⋅Ts
VCb
Ip
I
f
m1
N ⋅ m1
I ppk
I fpk
m2
I bus
N ⋅ m2
If
V0
V
s
t0
t2
t1
t3
to +Ts
to
Fig. 3.3. Typical ZVSFB PWM converter waveforms in DCM.
65
t
The average circuit model shown in Fig. 3.4(b) includes transformer’s leakage
inductance reflected to the secondary side to highlight its dynamic effects, which are
implicitly included in (3.20). The model becomes equivalent to that in Fig. 3.4(a) if Veq is
computed to make V2 appear in between the two inductors, that is, to have the same
average voltage delivered to the output filter. Therefore Veq is given by
Veq =
Vin
⋅ Dtrf +
N
V0 ⋅
Llk
N 2 ⋅ (1 − D ) .
ch
Lf
(3.21)
Fig. 3.4 indicates that controlled current source I1 corresponds to one cycle
average bus current. From Figs. 3.1(b) and 3.2, I1 can be computed as
I 1 = I bus =
(− I
)
(
)
+ I 1p
I p + I 2p
⋅ Dch + 1
⋅ Dtrf .
2
2
p
0
(3.22)
Calculation of Dtrf is again carried out on line in the simulator by closing the loop
around operational amplifiers to find the root located between 0 and Don. Equations (3.1)
through (3.22) can be combined to find the expression with Dtrf as the only unknown or
they can be arranged to solve for as many of the unknown quantities as desired.
DCM. Onecycle average filter inductor current is now given by (3.14) and the
average circuit model is shown in Fig. 3.5(a). Since this situation its very similar to that
found in the buck converter model the value I f may be enforced by adjusting, in the
average circuit model shown in Fig. 3.4, controlled source V2, which in turn depends on
D2. Therefore filter inductor current can be treated the same as in the buck converter
model, i.e. a loop around an operation amplifier that enforces algebraic constraint (3.14).
Bus current, according to (3.12) and Figs. 3.2 and 3.4 is given by
I1 =
I fpk ⋅ Don
2
m2 ⋅ (Don ) ⋅ Ts
.
=
2
2
(3.23)
3.2.5. Step 5: Calculation of algebraic constraints
These constraints are already described in (3.1) through (3.23) both for CCM and
DCM operation.
3.2.6. Step 7: Implementation of circuit oriented simulation
Fig. 3.6 shows the same technique used in Chapter 2 to compute, in real time
during the simulation, Dtrf and D2 both in CCM and DCM for the average model.
66
3.3.
Previous Average Models for the ZVSFB Converter
Models presented in [T4, V5] used the PWM switching model in [V8]. However
[T4, V5] neglects some effects of transformer’s leakage inductance upon rectifier’s
output voltage and upon filter inductor current slopes. As a result this average model
neither makes a smooth transition between CCM and DCM nor gives an accurate smallsignal model through linearization.
[V5] does not provide a large signal average model but only a DC (steadystate)
model and a smallsignal model is developed by adding some controlled sources to the
smallsignal model, derived through the PWM switching model in [V8], for the Buck
converter. It also neglects some effects of transformer’s leakage inductance upon
rectifier’s output voltage and upon filter inductor current slopes.
None of these models follows the correct introduction order for perturbation and
steadystate constraints pointed out in [V3] and hence validityrange of derived smallsignal models gets compromised.
3.4.
Simulation Results
New and previous [T4] average models of the ZVSFB PWM dcdc converter get
compared to its switching model through transient simulations. These simulations are
carried out for several sets of parameter values similar to those used in [V5], which are
listed in Table 1. Commanded dutyratio Don for all simulation is shown on top graph of
Fig. 3.23. Appendix B contains templates for the Saber simulator.
State variables from the new average model very closely follow moving average
of their respective counterparts in the switching model for all parameter sets, Figs. 3.7
through 3.20, whereas state variables from previous model can only exhibit good tracking
under special conditions, Figs. 3.14, 3.17 and 3.19, and can present faster or slower
dynamics than that of the switching model depending of operating conditions, Figs. 3.9,
3.11, 3.14 and 3.190. Furthermore the new average model maintains excellent tracking
during transient regimes that go back and forth between CCM and DCM as Figs. 3.8, 3.9,
3.10, 3.13, 3.16, 3.17 and 3.18 show.
3.4.1. Transient simulations for parameter set 1
Simulations results for this set are shown in Fig. 3.8 through 3.10. Even though
the ratio of filter inductance to transformer’s leakage inductance is 60 and hence effects
of the latter upon average behavior might be assumed negligible, as the previous model
[T4] does, Figs. 3.8 through 3.10 indicate that those effects are still relevant. The new
model maintains excellent state variables tracking for back and forth transitions between
CCM and DCM operating modes whereas the previous model [T4] lacks it due to the
loose approximation to model leakage inductor influence as Fig. 3.7, 3.9 and 3.10 clearly
show. The large inrush current shown in Figs. 3.7 and 3.8, not allowed in practice by the
67
startup sequence, was used here to solely illustrate average circuit model tracking
properties. Commanded dutyratio Don for all simulation is shown on top graph of
Fig. 3.19. Figs. 3.7 and 3.8 show responses to zero initial conditions for all models.
Table 1 Parameter value sets for transient
response of ZVSFB converter.
Parameter
Set 1
Set 2
Set 3
Set 4
Set 5
Turns Ratio
5
1
1
5
1
Leakage Induc. [µH ]
5
30
5
5
30
Filter Induc. [µH ]
12
30
12
12
100
Filter Cap. [µF ]
100
100
100
200
100
Load Resist. [Ω ]
20
75
5
10
75
Lf/(Llk/N2)
60
1
2.4
60
3.33
Vin [V ]
600
600
600
600
600
3.4.2. Transient simulations for parameter set 2
Simulation results for this set are shown in Fig. 3.11 through 3.13. The ratio of
filter inductance to transformer’s leakage inductance is 1 and hence effects of the latter
upon average behavior are very strong, contrary to what the previous model assumes.
Fig. 3.12 clearly shows three different slopes on inductor current waveforms, as
considered by the new model derivation above, and very close tracking characteristics of
the new model for transitions between CCM and DCM operating modes. In contrast to
this the previous model completely lacks tracking. Furthermore the previous model
exhibits slower dynamics than the correct one for certain operating conditions during the
transient and faster dynamics than the correct one for other operating conditions. As a
result the previous model cannot be used either for transient or stability analysis.
68
3.4.3. Transient simulations for parameter set 3
Figures 3.14 through 3.16 show simulation results for this special set of parameter
values. The latter were selected so that the steady state part of the simulation from the
previous average model matched very well results from the other two models but the fast
transients show not so good an agreement. Since results from previous average model for
set 2 showed faster and slower than correct dynamics it seemed possible to get a correct
response for certain range of parameter values and operating conditions. Obviously this
example warns about apparent good results when the ratio filter inductance to reflected
leakage inductance is relatively low. The same excellent tracking is observed for the new
model.
3.4.4. Transient simulations for parameter set 4
Figures 3.20 and 3.21 show simulation results for another special set of parameter
values. The latter were selected very similar to set 1, i.e. large ratio of filter inductance to
reflected leakage inductance, but to provide smooth transition between CCM and DCM
for the previous average model and to coincide with the other two models. These results
highlight the region of validity for the previous model. Once again the new model shows
excellent tracking.
Table 2. Parameter value set I for smallsignal model and transient
response of Buck, ZVSFB and ZVZCSFB converters.
Parameter
Buck
ZVS
ZVZCS
Turns Ratio
NA
6
6
Leakage Induct. [µH ]
NA
1
1
Blocking Cap. [µF ]
NA
20
1
Filter Induc. [µH ]
2
2
2
Filter Cap. [µF ]
200
200
20
Ω
1.1
1.1
1.1
Saturable Reactor [µV − sec]
NA
NA
60
Vin [V ]
55
330
330
Load Resist.
69
Table 3. Parameter value set II for smallsignal model and transient
response of Buck, ZVSFB and ZVZCSFB converters.
Parameter
Buck
ZVS
ZVZCS
Turns Ratio
NA
1
1
Leakage Induct. [µH ]
NA
1
1
Blocking Cap. [µF ]
NA
20
1
Filter Induc. [µH ]
20
20
20
Filter Cap. [µF ]
50
50
50
Ω
2.2
2.2
2.2
Saturable Reactor [µV − sec]
NA
NA
60
Vin [V ]
330
330
330
Load Resist.
3.4.5. Transient simulations for parameter set 5
Figures 3.22 and 3.23 show simulation results for another special set of parameter
values. Now the latter were selected very similar to set 2, i.e. low ratio of filter
inductance to leakage inductance. However the results look quite different from those for
set 2 since good tracking is seem from the previous average model. Here the new average
model also exhibited excellent tracking.
3.4.6
Transient and smallsignal simulation results.
Results from transient and linearization, within the same circuit simulator, for the
average model with two different resistive load values are shown in Figs. 3.21 through
3.24 for Buck, ZVS and ZVZCS converters. The latter, thoroughly analyzed in chapter 4,
is included here to highlight the contrast between the two softswitched converters with
respect to the damping added to the output filter. The transfer functions shown in Figs.
3.22 and 3.24, are Don to filter inductor current and Don to capacitor voltage. In the buck
70
converter these transfer functions have the same shape, i.e. pole frequency and damping,
as those from output low pass filter except for a different gain factor. Both ZVSFB and
ZVZCSFB converters alter output filter damping coefficient and pole frequency. These
changes depend on parameters values and/or operating conditions for both ZVSFB and
ZVZCSFB converters. With parameter value Set I in Table 2 both softswitched
converters change the damping factor by a fairly large amount albeit in opposite
directions. For the other parameter value set the ZVZCSFB converter exerts a very small
reduction in damping whereas the ZVSFB converter introduces a large increment.
71
72
V2
If
 Vo
V2
If
Lf
 Vo
RL
RL
Vs
If
I bus
to +Ts
V2 = Vs (t )
c) Waveforms for controlledsource average
calculation
I 1 = I bus (t )
to
V2
I1
Fig.3.4. ZVS converter equivalent average models and waveforms in CCM.
b) Mixed inputoutputinternal structure
model
Veq
Llk /N2
a) Inputoutput structure model
+ I1
Vin + I1
Vin
Lf
t
73
Vin
I2
+
 Vo
RL
Vs
to +Ts
I 2 = I f (t )
c) Waveforms for controlledsource average
calculation
I 1 = I bus (t )
to
vo
I2
I1
Fig.3.5. ZVS converter equivalent average model and waveforms in DCM.
a) Inputoutput structure model
+ I I1
If
I bus
t
Limiter
D2
Out
1 − Dtrf
In
m2
Eqn (3.4)
D2 ⋅ m2 ⋅ Ts − i
=0
pk
f
C
zero
R
_
OP
+
...
Z=
D
On
I
f
V
in
V
o
m3
Eqn (3.16)
C
Don − Dch − Dtrf = 0
Dtrf
zero
R
_
OP
+
Out
Don
In
Limiter
Fig. 3.6. Analog schematic for computation of Dtrf and D2.
74
Proposed
Model
Previous
Model
Previous
Model
Switching and Proposed
Model (Overlapped)
Lf
N 2 ⋅ Llk
= 60
Fig. 3.7. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average(black) models for parameter set 1
with zero initial state for all models.
75
Previous
Model
Proposed
Model
Previous
Model
Proposed Model
Switching Model
Lf
N 2 ⋅ Llk
= 60
Fig. 3.8. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 1
with zero initial state for all models.
76
Previous
Model
Proposed
Model
Previous
Model
Switching and Proposed
Model (Overlapped)
Lf
N ⋅ Llk
2
= 60
Fig. 3.9. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 1
with zero initial state for all models.
77
Previous
Model
Proposed
Model
Previous
Model
Switching and Proposed
Model (Overlapped)
Lf
N ⋅ Llk
2
= 60
Fig. 3.10. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 1
with zero initial state for all models.
78
Previous
Model
Proposed
Model
Previous
Model
Switching and Proposed
Model (Overlapped)
Lf
N 2 ⋅ Llk
=1
Fig. 3.11. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 2
with zero initial state for all models.
79
Previous
Model
Proposed
Model
Switching
Model
Previous
Model
Proposed
Model
Switching
Model
Lf
N 2 ⋅ Llk
=1
Fig. 3.12. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 2
with zero initial state for all models.
80
Previous
Model
Proposed
Model
Lf
Previous
Model
N 2 ⋅ Llk
=1
Switching and Proposed
Model (Overlapped)
Fig. 3.13. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 2
with zero initial state for all models.
81
Proposed
Model
Previous
Model
Switching and Proposed
Model (Overlapped)
Previous
Model
Lf
N 2 ⋅ Llk
= 2.4
Fig. 3.14. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 3
with zero initial state for all models.
82
Proposed
Model
Previous
Model
Switching
Model
Proposed
Model
Previous
Model
Lf
N 2 ⋅ Llk
= 2.4
Previous
Model
Fig. 3.15. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 3
with zero initial state for all models.
83
Previous
Model
Proposed
Model
Lf
N 2 ⋅ Llk
= 2.4
Proposed
Model
Switching and Proposed
Model (Overlapped)
Fig. 3.16. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 3
with zero initial state for all models.
84
Previous and Proposed
Model (Overlapped)
Previous, Proposed and
Switching Model
(Overlapped)
Lf
N 2 ⋅ Llk
= 60
Fig. 3. 17. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 4
with zero initial state for all models.
85
Previous and Proposed
Model (Overlapped)
Previous, Proposed and
Switching Model
(Overlapped)
Lf
N 2 ⋅ Llk
= 60
Fig. 3.18. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 4
with zero initial state for all models.
86
Commanded Duty
Cyacle)
Proposed
Model Dtrf
Proposed
Model D2
Proposed
Model
Previous
Model
Switching and Proposed
Model (Overlapped)
Previous
Model
Lf
N 2 ⋅ Llk
= 3.3
Fig. 3.19. Duty ratios (top), filter inductor current (middle) and capacitor voltage
(bottom) from switching (green), new average (pink) and previous average (black)
models for parameter set 5 with zero initial state for all models.
87
Commanded Duty
Cyacle)
Proposed
Model Dtrf
Previous
Model
Proposed
Model
Lf
Switching and Proposed
Model (Overlapped)
N ⋅ Llk
2
= 3.3
Previous
Model
Fig. 3.20. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 5
with zero initial state for all models.
88
Buck
ZVSFB
ZVZCSFB
ZVZCSFB
Buck
ZVSFB
Fig. 3.21. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set I.
89
Buck
ZVZCSFB
ZVSFB
Buck
ZVSFB
ZVZCSFB
Buck
ZVZCSFB
ZVSFB
Buck
ZVSFB
ZVZCSFB
Fig. 3.22. Capacitor voltage (top) and filter inductor current (bottom) transfer
functions from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set I.
90
Buck
ZVZCSFB
ZVSFB
Buck
ZVZCSFB
ZVSFB
Fig. 3.23. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set II.
91
ZVZCSFB
Buck
ZVSFB
Buck
ZVSFB
ZVZCSFB
ZVZCSFB
Buck
ZVSFB
Buck
ZVSFB
ZVZCSFB
Fig. 3.24. Capacitor voltage (top) and filter inductor current (bottom) transfer
functions from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set II.
92
4. MODELING OF THE SATURABLE INDUCTOR
BASED ZVZCSFBPWM DCDC CONVERTER
The new procedure for the derivation of autonomous average circuit models given
in Chapter 2 is again complemented here and then applied to the ZVZCSFBPWM
converter to get its circuit average model, which is a new result.
Comparison of simulation results between average and switching model shows
that most of the average dynamics is preserved. Furthermore a smallsignal model is
derived through linearization of the new average model within the circuit simulator and
compared to those for buck and ZVS models.
4.1
ZVZCSFBPWM Converter Operation
The ZVZCSFB topology introduced in [C11], Fig. 4.1(a), and whose switch
structures and typical waveforms for CCM operation are shown in Fig. 4.1(b) and 4.2,
respectively, operates with zerovoltage switching in the leading leg and zerocurrent
switching in the lagging leg for very wide load and line ranges. Although initially
intended to have its lagging leg built with IGBTs, the latter’s switching speed limitations
prevent their application at very high frequencies, where MOSFETs become the only
choice. However, by having conduction losses in the primary side strongly reduced
through almost complete elimination of freewheeling stage in that side, the ZVZCS
topology can still provide high efficiency for wide line range even with MOSFETs.
Appendix C provides detailed design procedure for the converter as well as its
waveforms and their exact describing equations for CCM operation. In this chapter only
brief descriptions of waveforms relevant to the development of the averaged circuit
model and their simplified expressions are presented.
4.1.1. CCM operation
Fig. 4.1(b) shows major topological stages for CCM operation of the ZVZCS
converter, i.e. Blocking, Charging, Transfer, Resetting and Off, whose characteristics are
summarized below [C11]. Fig. 4.2 shows typical waveforms for bridge voltage, Vab,
primary current, Ip, bus current, Ibus, blocking capacitor voltage, Vcb, filter inductor
current, If, rectifier’s output voltage, Vs and output voltage, V0.
Assume the switching cycle starts with the blocking stage at to, when bridge
voltage Vab becomes positive and saturable reactor blocks any primary current, and ends
at t1 when the reactor gets saturated. The sum of input voltage and blocking capacitor
voltage determines the rate of change of flux in the saturable reactor. The change of flux
during this stage amounts to
93
94

Vin
+
S2
S1
a
S4
b
N:1
a) Circuit schematic
Vcb Ip
+ 
L s Cb Llk
S3

+
Vo
Vin +Vcb
N
Vin + Vcb
N
Vin + Vcb
N
Fig.4.1. ZVZCS converter

Vs If
+
Lf
2
2
2
2
Ibus /N
Llk /N
Ibus /N
Llk /N
Ibus /N
Llk /N
Ibus /N
Llk /N
2
If
If
Vs
If
Lf
If
Lf
If
Lf
Vs
Vs
Vs
Lf
Vs
Lf
RL
RL
RL
V0
Off
V0
RL
RL
Resetting
V0
Transfer
V0
Charging
V0
Blocking
b) Switch structures in CCM
VSA
Vin +Vcb
N
VSA
Vin + Vcb
N
I
Ibus /N
Llk /N
Vin + Vcpk
N sr
∆φ blk = (t1 − t0 ) ⋅
V + Vcpk
= (Dblk ⋅ Ts ) ⋅ in
N sr
,
(4.1)
where Dblk, Nsr and Vcpk are blocking stage dutyratio, saturable reactor number of turns
and peak blocking capacitor voltage, respectively. On the secondary side output voltage
determines rate of change in filter inductor current, m4 in Fig. 4.2, as
m4 =
V0
.
Lf
(4.2)
During charging stage, (t1,t2), the same rate of change applies to filter inductor
current whereas the change in primary current, after neglecting transformer’s
magnetizing current and second order terms in Taylor’s series expansion, is
approximately given by
V +V
I 2p = in cpk
LLk
(t2 − t1 )⋅ = (m1) ⋅ (Dch ⋅ Ts ) ,
(4.2)
where slope m1, shown in Fig. 4.3, is defined by the first bracket, Dch corresponds to
charging stage duty ratio and the remaining quantities are defined in Fig. 4.2.
At time instant t2 primary current and filter inductor current are related by
transformer’s turns ratio, i.e.
I 2f = I 2p ⋅ N ,
(4.3)
and they remain so through transfer stage, which ends at t3 with commanded dutycycle
Don.
Don ⋅ Ts = (t3 − t0 ) = (Dblk + Dch + Dtrf )⋅ TS .
(4.4)
Reflection of input voltage and transformer leakage inductance to the secondary
side leads to the equivalent circuit for this stage, Fig. 4.1(b). Change in the filter inductor
current, after neglecting blocking capacitor effects, is approximately given by
Vin
−V
N O
I −I =
Llk 2 + L f
N
f
3
f
2
⋅ (t3 − t2 )⋅ = ( N ⋅ m2 ) ⋅ (Dtrf ⋅ Ts ) ,
(4.5)
where slope N ⋅ m2 is defined by the first bracket and the other terms by Fig. 4.2.
Blocking capacitor voltage, Vcb, is neglected here to simplify the derivation and because
its contribution is very small as later simulation results confirm.
95
Vab
S 2 , S3
Off
Resetting
S2 , S4
Transfer
Blocking
Charging
S1 , S4
D on ⋅ T s
D on ⋅ T s
Vcpk
Vcb
Ip
I
V in
m2
m1
I
p
2
N ⋅ m2
I 3f
m4
f
m4
I bus
I 3p m3
I 2f
If
I 4f
Vs
Vo
t0 t1 t2
t3
t4
t5
t
t o + Ts
to
Figure 4.2. ZVZCSFB PWM primary and filter inductor current waveforms in CCM.
96
Resetting stage starts at t3 when bridge voltage Vab becomes zero and it ends when
primary current does the same at t4. Duration of this stage is given by
Ip
1
Llk
⋅ arcsin 3 ⋅
V
Llk ⋅ Cblk
cpk Cblk
t4 − t3 = Dres ⋅ TS =
.
(4.6)
Off stage begins at t4 when saturable reactor blocks any primary current by taking
Vcpk as its flux rate of change and it ends at (to+Ts) with half of primary switching cycle
when Vab becomes negative as shown in Fig. 4.2. During this stage the change in flux
across the saturable reactor is given by
∆φoff =
Vcpk ⋅ (1 − Don − Dres ) ⋅ Ts
N sr
,
(4.7)
which together with saturable reactor voltsecond blocking capability determines
blocking stage duration, i.e.
∆φ Blk = 2 ⋅ φ sat − ∆φOff ,
(4.8)
where ∆φblk is given by (4.1) and 2 ⋅ φsat is the voltsecond blocking capability of the
saturable reactor.
Expressions for peak blocking capacitor voltage, Vcpk , filter inductor current
average and ripple values, I L ≡ I f and ∆I f are calculated next to complete the set of
equations. An approximation to Vcpk value is obtained by looking at converter’s steadystate operation and by taking into consideration the relevance of each stage’s duration
upon change in the capacitor voltage. These voltage changes during transfer and resetting
stages are respectively approximated by
∆Vc−trf =
I L ⋅ Dtrf ⋅ Ts
N ⋅ Cb
(4.9)
and
∆Vc − res =
Vcpk
(I )⋅ D
⋅ Ts
.
2 ⋅ N ⋅ Cb
f
3
res
(4.10)
From Figs. 4.2 and 4.5, after neglecting voltage change during charging stage,
is given by
97
S 2 , S3
Off
Idling
Resetting
S2 , S4
Transfer
Blocking
S1 , S4
V in
Vab
D on ⋅ T s
D2 ⋅ T s
D on ⋅ T s
Vcpk
Vcb
I ppk
Ip
I
f
N ⋅ m2
I bus
m3
m2
I fpk
m4
If
Vo
Vs
t0 t1
t2
t3 t4 t5
t
t o + Ts
to
Figure 4.3. ZVZCSFB PWM primary and filter inductor current waveforms in DCM.
98
Vcpk =
∆Vc−trf + ∆Vc−res
2
.
(4.11)
On the other hand ∆I f is calculated as
∆I f = Dtrf ⋅ (I 3f − I 2f ) + (1 − Dtrf )⋅ (I 4f − I 3f ) ,
(4.12)
V
I 4f − I 3f = O
L
f
(4.13)
where
⋅ (1 − Dtrf )⋅ Ts = m4 ⋅ (1 − Dtrf )⋅ Ts .
4.1.2. DCM operation
Typical waveforms for DCM operation are shown in Fig. 4.3. Clearly there is no
charging stage and hence commanded duty cycle equals the sum of blocking and transfer
stages, i.e.
Don = Dblk + Dtrf .
(4.14)
Peak filter inductor current is given by
V / N −V
I fpk = in 2 0
L /N +L
f
lk
⋅ (t2 − t1 ) = ( N ⋅ m2 ) ⋅ (Dtrf ⋅ Ts )
(4.15)
V0
I fpk =
L / N2 + L
f
lk
⋅ (t3 − t2 ) = (m4 ) ⋅ (D 2 ⋅ Ts ) .
(4.16)
and by
One cycle average inductor current is calculated from (4.15) and (4.16) as
IL = I f =
I fpk ⋅ (Dtrf + D 2 )
2
,
(4.17)
which gives the same DCMCCM boundary condition as in the buck converter, i.e.
If =
I fpk
2
99
.
(4.18)
Equating (4.15) and (4.16) gives
D2 =
Dtrf ⋅ N ⋅ m2
(4.19)
m4
and its substitution into (4.17) gives the algebraic constraint on onecycle average
inductor current, i.e.
N ⋅ m2 ⋅ (Dtrf ) ⋅ Ts
N ⋅ m2
If =
.
1 +
2
m4
2
(4.20)
As in the Buck converter, this constraint indicates that onecycle average filter
inductor current is not an independent average state.
Equation (4.1) still applies during blocking stage and (4.7) now represents the
change in flux across the saturable reactor during the sum of intervals for off and idling
stages. On the other hand expressions for capacitor voltage, i.e. (4.9), (4.10) become
∆Vc −trf =
I fpk ⋅ Dtrf ⋅ Ts
2 ⋅ N ⋅ Cb
,
(4.21)
,
(4.22)
and
∆Vc −res =
I fpk ⋅ Dres ⋅ Ts
2 ⋅ N ⋅ Ccb
whereas (4.11) remains the same.
4.2.
New Average Circuit Model for the ZVZCSFB Converter
Systematic application of the new procedure leads to the inputoutput structure
average model of the ZVZCSFB PWM dcdc converter shown in Fig. 4.4(a) as detailed
next.
4.2.1. Step 1: Fast/slow classification of state variables
Figure 4.2 indicates that filter inductor current and output capacitor voltage qualify as
slow variables in CCM to be used as states in the average circuit model. However in
DCM only the output capacitor remains as a slow state. Similarly to the situation in
Chapter 3 filter inductor current stays at zero during a significant amount of time within a
switching cycle, which leads to having its onecycle average fully determined by present
switching cycle condition and hence being converted to a fast variable.
100
101
Vin + I 1
Vin
 Vo
Veq
Llk /N2
V2 I
Lf
IL
a) Input –output structure
V2
IL
 Vo
RL
RL
Vs
If
Ibus
Vab
to
to +Ts
Vin
V2 =Vs (t )
c) Typical waveforms
I1 = Ibus (t )
V2
I1
Fig.4.4. ZVZCS converter equivalent average models and waveforms in CCM.
b) Mixed inputoutputinternal structure
+ I1
Lf
t
Again primary current is discarded as a relevant average state variable, even
though it corresponds to leakage inductor state variable, because its moving average is
zero in steady state operation and exhibits large components at one half the switching
frequency and higher harmonics during transient regime. In other words no new
information would be provided in steady state and time varying effects would have to be
included in the model.
Blocking capacitor voltage gets classified as a fast variable and its waveform in
Fig. 4.2 indicates that it is an energy holding element. Its treatment is presented later in
this chapter.
4.2.2. Step 2: LTI input/output parts
Output filter and input voltage source get selected as LTI networks according to
circuit topologies in Fig. 4.1(b).
4.2.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network
From Fig. 4.1(b) it looks apparent that average bus current is the “Dependent
variable” drawn from input voltage source whereas secondary rectifier’s output voltage
is the “Independent variable” applied to the output filter during CCM operation. On the
other hand from Fig. 4.3 it is clear that one cycleaverage inductor current becomes the
sought Independent variable fed to the output section during DCM operation the same as
in the ZVSFB converter.
4.2.4. Step 4: Calculation of onecycle average for the variables in the previous step
CCM. According to Figs. 4.1(b), 4.2 and 4.4(c) rectifier’s voltage is a function of
input, blocking capacitor and output voltages during transfer stage, i.e.
L
Vin + Vcb
⋅ L f + V0 ⋅ lk2
N ,
N
Vs =
Llk
+ Lf
N2
(4.23)
whereas the rest of the switching cycle it becomes zero. From (4.23) and Fig. 4.2 the one
cycle average rectifier voltage can be expressed as
(V
in
Vs =
)
+ Vcb
L
⋅ L f + V0 ⋅ lk2
N
N ⋅D
trf
Llk
+
L
f
N2
102
(4.24)
Vcpk
Vcb
mcb
A2
0
A1
A3
Vcpk
Dtrf ⋅ Ts
IL
mcb ≈
N ⋅ Cb
Vcb =
A1

A2
Dtrf ⋅ Ts
Figure 4.5. Calculation of average blocking capacitor voltage.
103
where Vcb is the average of blocking capacitor voltage during transfer stage. According
to Fig. 4.5 Vcb is directly proportional to the difference between areas A2 and A1, i.e.
Vcb =
(V
cpk
Vcb =
A2 − A1 ( A2 + A3 ) − ( A1 + A3 )
=
Dtrf ⋅ Ts
Dtrf ⋅ Ts
Dtrf ⋅ T
I
⋅ Dtrf ⋅ Ts ) − L ⋅
I L ⋅ Dtrf ⋅ Ts
2
N ⋅ Cb
,
= Vcpk −
2 ⋅ N ⋅ Cb
Dtrf ⋅ Ts
(4.25.a)
(4.25.b)
where the slope of blocking capacitor voltage during transfer stage is approximated by
mcb ≈
IL
.
N ⋅ Cb
(4.26)
The average circuit model shown in Fig. 4.4(b) includes transformer’s leakage
inductance reflected to the secondary side to highlight its dynamic effects, implicitly
included in (4.25). As in the ZVSFB converter case Veq can be computed to make V2
appear in between the two inductors, that is, to have the same average voltage delivered
to output filter. Therefore Veq is given by
Veq =
Vin + Vcb
V ⋅L
⋅ Dtrf − 02 lk ⋅ (1 − Dtrf ).
N
N ⋅ Lf
(4.27)
Fig. 4.5 indicates that controlled current source I1 corresponds to one cycle
average bus current. From Figs. 4.2, and 4.4(c) I1 can be computed as
I 1 = I bus =
(
)
I P2
I 2 + I P3
⋅ Dch + P
⋅ Dtrf .
2
2
(4.28)
DCM. Onecycle average filter inductor current is now given by (4.17). Since this
situation is the same as that found both in the buck and ZVSFB converter models the
value I f must be enforced by adjusting, in the average circuit model, controlled source
V2, which in turn depends on D2. Therefore filter inductor current can be treated the same
as in the previous two converter models, i.e. a loop around an operation amplifier that
enforces algebraic constraint (4.17).
Calculation of Dtrf is again carried out on line in the simulator by closing the loop
around operational amplifiers to find the root located between 0 and Don. Equations (4.1)
104
through (4.29) can be combined to find an expression with Dtrf as the only unknown or
they can be arranged to solve for as many of unknown quantities as desired.
Bus current, according to (4.15) and Fig. 4.3 is given by
I1 =
I Fpk ⋅ DTrf
2⋅ N
=
m2 ⋅ (DTrf
2
)
2
⋅ Ts
.
(4.29)
4.2.5. Step 5: Calculation of algebraic constraints
These constraints are already described in (4.1) through (4.22) both for CCM and
DCM operation.
4.2.6. Step 7: Implementation of circuit oriented simulation
Fig. 4.6 shows the same technique used in the previous two chapters to compute,
in real time during the simulation, Dtrf and D2 both in CCM and DCM for the average
model.
4.2.7. Identification and modeling of energy holding elements in fast dynamic
subsystems
An energy holding element is a reactive component that does not appear as a
relevant state in the average model and its state variable (voltage for capacitors, current
for inductors):
a)
b)
c)
d)
e)
gets classified as fast type.
has zero moving average in steady state operation and exhibits large
components at one half the switching frequency and higher harmonics
during transient regime.
exhibits relatively large peaktopeak excursions.
exhibits nonzero and relatively large constant value during a significant
time interval within a switching cycle.
exerts a significant influence upon switching instants and/or
“Dependent/Independent” controlled sources’ onecycle average value.
Since this state variable is the integral of a piecewise continuous function it is
continuous and from (a) and (b) its temporary nonzero constant value depends on the
history of that integrand, in general a function of some state variables. Because of (d) this
“nonzero constant value” is a critical parameter in the converter constraint equations and
its dynamics must be appropriately modeled. Sample data models can very easily and
accurately describe these effects whereas high order average continuous models need be
used for the same accuracy.
105
Limiter
Out
D2
1DTrf
In
m1
Eqn (4.2)
D2 ⋅ m2 ⋅ Ts − i Lpk = 0
C
zero
R
_
OP
+
C
...
Z=
D
On
I
f
V
in
V
C
m2
Eqn (4.5)
DOn − DBlk − DCh − DTrf = 0
zero
DTrf
R
_
OP
+
Out
1
In
Limiter
Figure 4.6. Analog computation of Dtrf and D2.
106
R=
Ts
C
Limiter
C
IL
R
_
OP
+
Out
D2
− I L− slow
1DTrf
In
I L − slow ⋅ Dtrf ⋅ Ts /N ⋅ C b
Z=
D
On
I
L
Vin
V
C
(I )⋅ D
f
3
res ⋅ Ts /2 ⋅ N ⋅ C b
D2 ⋅ m2 ⋅ Ts − i Lpk = 0
I L− slow + ∆I L /2
DOn − DBlk − DCh − DTrf
∆Vc − trf
∆Vc − Res
zero
C
R
_
OP
+
I 3f
zero
DTrf
C
R
_
OP
+
Out
1
In
Limiter
Figure 4.7. Analog implementation of dynamic relationship between filter inductor
current an blockingcapacitor peak voltage .
107
Here a heuristic approach is followed to obtain a simple and effective
representation of this energy holding element effects. Circuit simulations verify
usefulness of this representation.
In our ZVZCSFB converter blocking capacitor reaches Vcpk at the end of
resetting stage and holds it constant until the end of blocking stage. Duration of the latter
is inversely related to Vcpk and hence to the long history of IL whereas that of charging
stage is directly related to IL in the present switching cycle. As a consequence, an
intricate relation among circuit parameters determines whether positive or negative
damping is added to the output filter as summarized next and explained in more detail in
Appendix C for steadystate operation.
The change in damping is directly related to the loss of dutycycle,
Don − Dtrf = Dblk + Dch ,
(4.30)
and hence inversely related to the change in transfer stage duty ratio. Since duration of
the charging stage, i.e. Dch, is proportional to IL the change in duration of blocking stage
with respect to IL has to overcome that in Dch for damping of the output filter to get
reduced (intrinsic positive feedback). A low Cblk value in the ZVZCS converter, as
compared to that in the ZVS converter, leads to a large change in Vcpk with IL. This in turn
makes the product Vcpk ⋅ Doff ⋅ Ts bigger, which produces a reduction in blocking stage
duration, since saturablereactor voltsecond blocking capability is constant. The size of
that reduction will strongly depend on blocking capacitor value and saturable reactor
voltsecond blocking capability. Furthermore, it is possible to have an increase in dutycycle loss for some component values, especially when they resemble those used in the
ZVS converter.
Moreover, the amount of damping added to the output filter in the average model
is strongly dependent on the type of relationship representation, i.e. algebraic o dynamic,
between Vcpk and IL as transient simulation results in Figs. 4.8 through 4.10 show. These
results, for parameter value Set 1 in Table 4, correspond to a switching model, a
simplified average model and the proposed average model. The simplified average model
uses a standard algebraic equation whereas the proposed average model approximates the
relationship between Vcpk and IL as dynamic through a single time constant equal to a
switching semicycle, Ts as shown in Fig. 4.7, i.e. IL is modified by a first order low pass
filter, whose output is labeled ILslow in Fig. 4.7, before been used in the computation of
Vcpk according to (4.9) through (4.11).
Clearly the simulation results in Fig. 4.8 through 4.10 indicate that the proposed
average model closely tracks moving average of switching model state variables whereas
the simplified model presents poor tracking due to its faster dynamics, i.e. equivalent pole
frequency and damping factor higher than actual ones. Only usefulness of the average
model with the dynamic constraint will be thoroughly verified through transient
simulations for different parameter set values.
108
Standard Approach
Proposed Model
Figure 4.8. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), first average (blue) and second average (pink) models for parameter set 1 with
zero initial state for all models.
109
Sta ndard Approach
Sta ndard Approach
Proposed M odel
Proposed and
Sw itching M odel
Proposed M odel
Sta ndard Approach
Sta ndard Approach
Proposed and
Sw itching M odel
Figure 4.9. Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter set 1 with
zero initial state for all models.
110
Standard Approach
Proposed Model
Figure 4.10. Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter set 1 with
zero initial state for all models.
111
4.3.
Simulation Results
State variables from the average model with the dynamic constraint very closely
follow moving average of their respective counterparts in the switching model for
different parameter value sets (Table 4) as Figs. 4.10 through 4.25 show.
Table 4. Parameter set values for transient simulations.
Parameter
Turns
Ratio
Leakage
Inductance
Blocking
Capacitor
Filter
Inductance
Filter
Capacitor
Load
Resistance
Saturable
Reactor
Set 1
Set 2
Set 3
Set 4
Set 5
Set 6
6
4
4
4
6
4
1 uH
2uH
2uH
2uH
1uH
1uH
1uF
0.5uF
0.5uF
0.5uf
1uF
2uF
2uH
8uH
8uH
3uH
2uH
2uH
200uF
50uF
50uF
33uF
200uF
50uF
1.1 Ω
1.1 Ω
3Ω
1.8 Ω
0.3 Ω
1.1 Ω
60 µ Vs
60 µ Vs
60 µ Vs
60 µ Vs
60 µ Vs
60 µ Vs
4.3.1. Transient simulations for parameter set 1
Simulations results for set 1 are shown in Figs. 4.11 through 4.14. This set of
parameters was calculated in a specific application design [20]. The load here was
selected to obtain a very lightly damped response with large oscillation amplitude while
still maintaining CCM operation since these conditions fully test the CCM model. State
variables of the proposed average model almost perfectly match the dynamics, i.e. pole
frequency and damping factor, of switchingmodel statevariable moving average for a
time interval over twenty times larger than the oscillation period, which is around
150 µ s. The oscillation amplitude of the average filter inductor current over the same
interval changes from 15A to 0.2mA, i.e. attenuation of 97dB. It is important to point out
that simulation time for the average model is still less than one tenth of that required by
the switching model for this type of agreement. The difference in pole oscillation
frequency between average model and switching model is around 1% according to the
phase difference seen at the end of the simulation interval in Fig. 4.14, i.e. phase shift less
than one quarter of a cycle after 20 cycles.
112
Average Model
Average Model
Average and
Switching Model
Figure 4.11. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 1
with zero initial state for both models.
113
Average Model
Average and
Switching Model
Average Model
Average and
Switching Model
Figure 4.12. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero initial state for
both models.
114
Average Model
Average and
Switching Model
Average Model
Average and
Switching Model
Figure 4.13. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero initial state for
both models.
115
Switching Model Crest Envelope
Average Model
Switching Model Valley Envelope
Switching Model Crest Envelope
Average Model
Switching Model Valley Envelope
Figure 4.14. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero initial state for
both models.
116
Moving average of filter inductor current was not calculated because of the
excellent agreement in output voltage. In other words, the only way for the capacitor
voltage in the average model to almost perfectly follow the moving average of the
capacitor voltage in the switching model is by receiving the same average filter inductor
current since the resistive loads are equal.
4.3.2. Transient simulations for parameter set 2
Simulations results for set 2 are shown in Figs. 4.15 and 4.16. All the parameter
values are different from those in set 1 but the load, which remained at 1.1 ohms.
Moreover these parameters were selected to produce a less lightly damped response than
the previous one with the same pole frequency. Consequently deep CCM operation is
seen. Again state variables of the proposed average model very closely match the
dynamics, i.e. pole frequency and damping factor, and steady state of switchingmodel
statevariable moving average over the transient interval and the subsequent time
respectively. Simulation time for the average model is again less than one tenth of that
required by the switching model for this type of agreement. Difference in outputvoltage
steadystate values between models is less than 1%.
4.3.3. Transient simulations for parameter set 3
Simulations results for set 3 are shown in Figs. 4.17 through 4.19. All the
parameter values are the same as those in set 2 but the load, which changed to 3 ohms.
Naturally a more lightly damped response than the previous one is obtained but deep
CCM operation is still seen. Once again state variables of the proposed average model
very closely match the dynamics, i.e. pole frequency and damping factor, and steady state
of switchingmodel statevariable moving average for a time interval over twenty times
larger than the oscillation period, which is around 150 µ s. It is important to point out that
simulation time for the average model is still less than one tenth of that required by the
switching model for this type of agreement. The difference in pole oscillation frequency
between average model and switching model is around 1% according to the phase
difference seen at the end of the simulation interval in Fig. 4.19, i.e. phase shift less than
one quarter of a cycle after 20 cycles.
4.3.4. Transient simulations for parameter set 4
Simulations results for set 4 are shown in Figs. 4.20 and 4.21. Output filter
component values and load resistor value are reduced with respect to those in set 3 so that
the response is almost critically damped. Similarly to the previous cases average
dynamics is very closely matched and simulation time for the average model is still less
than one tenth of that required by the switching model for this type of agreement. Output
voltage steady state error is again less than 1%.
117
Average Model
Average and
Switching Model
Figure 4.15. Whole transient filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 2 with zero
initial state for both models.
118
Average Model
Average and
Switching Model
Average Model
Switching Model
Switching Model
Average Model
Figure 4.16. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 2 with zero initial state for
both models.
119
Average Model
Average and
Switching Model
Figure 4.17. Whole transient of filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 3 with zero
initial state for both models.
120
Average Model
Average and
Switching Model
Average Model
Switching Model
Average Model
Figure 4.18. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero initial state for
both models.
121
Average Model
Switching Model
Average Model
Average Model
Average Model
Figure 4.19. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero initial state for
both models.
122
Average Model
Average and
Switching Model
Average Model
Average and
Switching Model
Figure 4.20. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 4
with zero initial state for both models.
123
Average Model
Switching Model
Average Model
Average Model
Switching Model
Switching Model
Average Model
Figure 4.21. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 4 with zero initial state for
both models.
124
4.3.5. Transient simulations for parameter set 5
Simulations results for set 5 are shown in Figs. 4.22 and 4.23. All the parameter
values are the same as in set 1 except for load resistor which gets reduced to 0.3 ohms.
The same as for set 1 average dynamics is almost perfectly matched and simulation time
for the average model is still less than one tenth of that required by the switching model
for this type of agreement.
4.3.6. Transient simulations for parameter set 6
Simulations results for set 5 are shown in Figs. 4.24 and 4.25. Except for leakage
and filter inductance values all the parameter values are changed. The same as for set 6
average dynamics is almost perfectly matched and simulation time for the average model
is still less than one tenth of that required by the switching model for this type of
agreement.
4.4.
Dynamics Comparison among Buck, ZVSFB and ZVZCSFB
Converters
4.4.1. Transient response and smallsignal transfer function from new average
model and its linearization
Results from linearization and their respective transient simulations, already
presented in Chapter 3, are reproduced here in Figs. 4.26 through 4.29 for further
analysis.
As already pointed out in Chapter 3 transfer functions in Figs. 4.27 and 4.29 show
that the amount of damping added to output filter and of reduction in its pole frequency
depends on parameters values and/or operating conditions for both ZVSFB and ZVZCSFB converters. With parameter value Set I both softswitched converters change the
damping factor by a fairly large amount albeit in opposite directions. For the other
parameter value set the ZVZCSFB converter exerts a very small reduction in damping
whereas the ZVSFB converter introduces a large increment.
Transient responses in Fig. 4.26 for parameter Set I show that voltage conversion
ratio, i.e. output voltage, is larger in the ZVSFB converter whereas Fig. 4.28 shows the
opposite for parameter Set II.
From these observations it looks likely for the ZVZCSFB converter to add either
positive or negative damping to the output filter depending on parameter values and
operating conditions as Appendix C explains in more detail.
125
4.4.2. Smallsignal experimental results
Figure 4.30 shows experimental voltage to output transfer function for Buck and
ZVZCSFB converters for parameter value Set I. Peaking for ZVZCSFB converter is
higher than that for the Buck converter as predicted by the smallsignal average model.
Differences between experimental and simulation results are mostly due to idealization of
components, i.e. neglect of parasitics, hysteresis and tolerances.
126
Average Model
Average and
Switching Model
Average Model
Average and
Switching Model
Figure 4.22. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 5
with zero initial state for both models.
127
Average Model
Switching Model
Average Model
Average Model
Switching Model
Switching Model
Average Model
Figure 4.23. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 5 with zero initial state for
both models.
128
Average Model
Average and
Switching Model
Average Model
Average and
Switching Model
Figure 4.24. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 6
with zero initial state for both models.
129
Average Model
Switching Model
Average Model
Switching Model
Average Model
Switching Model
Average Model
Figure 4.25. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 6 with zero initial state for
both models.
130
B uck
Z V S F B
Z V Z C S F B
Z V Z C S F B
B u ck
Z V S F B
Figure 4.26. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set I.
131
Buck
ZVZCSFB
ZVSFB
Buck
ZVSFB
ZVZCSFB
Buck
ZVZCSFB
ZVSFB
Buck
ZVSFB
ZVZCSFB
Figure 4.27. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red), ZVSFB (blue)
and ZVZCSFB (black) converters with parameter set I.
132
Buck
ZVZCSFB
ZVSFB
Buck
ZVZCSFB
ZVSFB
Figure 4.28. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVSFB (blue) and ZVZCSFB
(black) converters with parameter set II.
133
ZVZCSFB
Buck
ZVSFB
Buck
ZVSFB
ZVZCSFB
ZVZCSFB
Buck
ZVSFB
Buck
ZVSFB
ZVZCSFB
Figure 4.29. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red), ZVSFB (blue)
and ZVZCSFB (black) converters with parameter set II.
134
50
ZVZCS
Magnitude (db)
40
30
BUCK
20
10
0
Phase (deg)
60
0
60
ZVZCS
BUCK
120
1
10
100
Frequency (kHz)
Figure 4.30. Experimental control to capacitor voltage (top) transfer for Buck and
ZVZCSFB converters with parameter set II.
135
5.
MODELING AND MODULATION FOR QSSZVZCS
THREEPHASE BUCK RECTIFIER
The new procedure and the average model for the ZVZCSFBPWM dcdc
converter from the previous chapter are extended here to develop a counterpart for the
QuasiSingleStage (QSS) ZVZCS threephase buck rectifier shown in Fig. 5.1(a).
Average steadystate operation occurs over one line voltage cycle, e.g. 60Hz, and hence
average along the switching frequency orbit to obtain autonomous average model, as in
previous chapters, no longer applies. Nevertheless, the average model still can represent
most of the rectifier’s dynamics and can be used for stability analysis.
Assuming that closedloop bandwidth dynamics is much faster than line
frequency allows us to consider the QSSZVZCS rectifier as operating in a quasisteadystate tracking condition. This new average model revealed strong nonlinear relations
between applied and effective dutycycles of standard space vector modulation (SVM).
Those nonlinearities are the source of increased input current distortion and output
voltage ripple. If these were left to be solely counteracted by the feedback loop, the latter
would have to exhibit very large bandwidth, which is already constrained by the
switching frequency.
Based on insight provided by the development of the average model, a new
modulation scheme together with feedforward dutycycle compensation is proposed to
effectively minimize output voltage ripple with slight ac current distortion, while
allowing use of the same singleloop control strategy. Experimental results verify average
model predictions as well as modulation and dutycycle compensation scheme efficacy.
5.1
ThreePhase Buck Rectifier
Operation of the threephase PWM buck rectifier, Fig. 5.2(a) is reviewed first to
help desription of its synchronization with the ZVZCSFB converter.
According to the nature of the input and output variables (currents and voltages)
and the direction of energy flow, three phase converters can be classified as current
source or voltage source rectifiers or inverters. The input variables of the buck rectifier
are the three phase input voltages and the dc current source. The output variables are the
dc link voltage and the threephase AC input currents. Hence the buck rectifier can be
also viewed as a Voltage Source Rectifier. The process of synthesizing the low frequency
output variables of the converters could be described as follows [H3, N3]:
136
137
S bn
San
Vb
Vc
S2
n
x
L sa
S4
y
N:1
D2
D1

+
Vs
ZVZCS FB Converter
(Phase Shifted Modulation)
Ip
C blk L lk
S3
Fig.5.1. QSSZVZCS threephase rectifier
Scn
S cp
Buck Rectifier
(SVM)
Va
Sbp
S ap
S1
p
I Lf
Lf

+
Vo
Sap
ia
Va
Vb
Vc
Sbp
Scp
ib
San
Sbn
p
ic
I
Scn
n
a) Simplified threephase buck rectifier structure
Sbn
Sap
Scn
Sbp
vb
va
0
0
Sector 6
600
Sector 1
San
0
120
Sector 2
1800
Sector 3
Scp
vc
2400
Sector 4
3000
Sector 5
b) Input phase voltage determines 600 electric sectors and the corresponding
switch that is alwayson throughout the sector
Fig. 5.2. Threephase buck rectifier and electric sectors.
138
For a set of input voltages,
v a = Vm cos( ωt + ϕ ),
vb = Vm cos( ωt − 2π 3 + ϕ ),
(5.1)
vc = Vm cos( ωt − 4π 3 + ϕ ),
output current,
io = I ,
(5.2)
desired set of input currents,
ia = I m cos( ωt + θ ),
ib = I m cos( ωt − 2π 3 + θ ),
(5.3)
ic = I m cos( ωt − 4π 3 + θ ),
and desired dc link voltage,
Vout = V pn ,
(5.4)
determine the control law requirements for the switches of the frontend rectifier.
The sixstep modulation of the threephase PWM buck rectifier is described in the
following with reference to Fig. 5.3. Due to voltage sources on the AC side and current
sources on the DC side of the rectifier, the converter switches can assume only six
allowable combinations that yield nonzero phase currents and three combinations that
yield zero phase currents. In space vector representation, the input phase currents are
therefore synthesized from 7 discrete current vectors I0 to I6, also called current switching
state vectors (SSVs). The set of SSVs that yield nonzero phase currents form the VSR
hexagon as shown in Figure 5.3(a). The parenthesized symbols in the VSR Hexagon
represent the switches that are conducting during the synthesis of the respective current
vector. The triangular area between two adjacent space vectors is called a sector and it is
analog to the sectors in Fig. 5.2 (b). The space vector of the desired phase currents iref,
called the reference vector, can be synthesized as a time weighted average of the two
adjacent nonzero SSVs and an appropriate zero SSV over a switching cycle Ts. Since
the operation of the converter within the sectors has circular symmetry, the duty cycles of
the three SSVs belonging to a sector that are used for the synthesis of the reference vector
over a switching cycle are given by:
d 1 = m ⋅ sin( 60 0 − θ i ),
d 2 = m ⋅ sinθ i ,
d0 = 1 − d1 − d 2
139
(5.5)
140
Va
Vb
Vc
San
ia
Sap
5
I5 (Scp , San)
4
I4 (Sbp , San ) 3
6
iref
1
I1 (Sap , Sbn )
I2 (Sap , Scn )
1
d1 I
d 2I 2
Sbn
ib
Sbp
Scn
ic
Scp
I1
I
San
ia
Sbn
ib
Scn
ic
Scp
I
I1
n
p
00
θi
duty cycle i
duty cycle ii
600
Va
Vb
Vc
San
ia
Sap
Sbn
ib
Sbp
Scn
ic
Scp
I0
I
n
p
b) Normalized dutycycle variation
within electric sector 1
0
0.5
0.866
a) Circuit topologies for electric sector 1
Va
Vb
Vc
Sap
I2
iref
I2
Fig.5.3. Threephase buck rectifier with standard SVM
n
p
Sbp
θi
a) SVM hexagon and vector synthesis
I6 (Scp , Sbn )
Io
2
I3 (Sbp , Scn )
141
0.5
0
0.5
10
0
10
60 0
d2
d1
Vo
Rail
Voltage
Phase
Currents
Vab
d2
c) Pulsed waveforms
Vpn
ia
ic
ib
Fig.5.4. Threephase buck rectifier ideal SVM operation
a) Normalized duty cycles
0
0
.867
.867
b) Ideal phase currents (Amp)
and output voltage ripple (Volt)
10
0
d1
Vac
IfL
where d1, d2 and θi are shown in Figure 5.3(a) and (b) and 0 0 ) {
ipk = vilf + delta_ilf
}
else {
if ( vdeltaup  vdeltadwn > 0 ) {
ipk = vilf + delta_ilf
}
else {
ipk = 2*vilf/(vd1+vd2+1e7)
}
}
v_vequiv = vvin*vd1/(vd1+vd2+1e7)
v_iequiv = vilf*vd1/(vd1+vd2+1e7)
v_zeros = Ts*vd2*vvout  ipk*Lf
}
# end of values section
equations {
i(zeros>com) += i_zeros
i_zeros : v(zeros)  v(com) = v_zeros
i(i_equiv>com) += i_iequi
194
i_iequi : v(i_equiv)  v(com) = v_iequiv
i(v_equiv>com) += i_vequi
i_vequi : v(v_equiv)  v(com) = v_vequiv
}
} # end of equations section
# end of template body
195
196
Fig.A.1. Saber schematics for Buck converter
B
Listing of Saber templates for ZVSFB PWM Converter
Average Models
B1.
Previous Model
element template zvs_duo_PREVIOUS com ilf vout vin Don Dtrf
D2 i_equiv v_equiv i_deviat zero_Dtrf zero_D2 = Ts, Lf,
Llk, N
electrical com, ilf, vout, vin, Don, Dtrf, D2, i_equiv,
v_equiv, i_deviat, zero_Dtrf, zero_D2
number Ts, Lf, Llk, N
{
val v delta_ilf, ipk, d_off, vilf, vvout, vvin, vDon,
vDtrf, vDoff, VDch, vD2,
v_vequiv, v_iequiv, v_ideviat, v_zero_D2,
v_zero_Dtrf, vdeltaup, vdeltadwn, Lequiv, NTS
var i i_iequi, i_vequi, i_ideviat, i_zero_D2, i_zero_Dtrf
values {
vilf = v(ilf)v(com)
vvout = v(vout)v(com)
vvin = v(vin)v(com)
vDon = v(Don)v(com)
vDtrf = v(Dtrf)v(com)
vD2
= v(D2)v(com)
Lequiv = Lf + Llk/N**2
vDoff = 1  vDtrf
NTS
= N*Ts
vdeltaup = vDtrf*(vvin/Nvvout)*Ts/Lequiv
delta_ilf = vdeltaup/2
if (vilf  delta_ilf/2 > 0 ) {
ipk = vilf + delta_ilf
197
vDch = (Vilf)*2*Llk/vvin/NTS
}
else {
ipk = 2*vilf/(vDtrf+vD2+1e7)
vDch = 0
}
v_ideviat = vDch*(vilf)
v_vequiv = vvin*vDtrf/(vDtrf+vD2+1e7)/N
v_iequiv = vilf*vDtrf/(vDtrf+vD2+1e7)/N
v_zero_D2 = Ts*vD2*vvout  ipk*Lf
v_zero_Dtrf =  vDon + vDch + vDtrf
}
# end of values section
equations {
i(zero_D2>com) += i_zero_D2
i_zero_D2 : v(zero_D2)  v(com) = v_zero_D2
i(zero_Dtrf>com) += i_zero_Dtrf
i_zero_Dtrf : V(zero_Dtrf)  v(com) = v_zero_Dtrf
i(i_equiv>com) += i_iequi
i_iequi : v(i_equiv)  v(com) = v_iequiv
i(i_deviat>com) += i_ideviat
i_ideviat : v(i_deviat)  v(com) = v_ideviat
i(v_equiv>com) += i_vequi
i_vequi : v(v_equiv)  v(com) = v_vequiv
}
}
#
end of equations section
# end of template body
198
B2.
New Model
element template zvs_duo_2_rev2_4a com ilf vout vin Don
Dtrf D2 i_equiv v_equiv i_deviat zero_Dtrf zero_D2 I1out
I3out = Ts, Lf, Llk, N
electrical com, ilf, vout, vin, Don, Dtrf, D2, i_equiv,
v_equiv, i_deviat, zero_Dtrf, zero_D2, I1out, I3out
number Ts, Lf, Llk, N
{
val v delta_ilf, deltaup, deltadwn, ipk, d_off, vilf,
vvout, vvin, vDon, vDch, vDtrf, vDoff, vD2,vDtrf1, AA, BB,
CC,
v_vequiv, v_iequiv, v_ideviat, v_zero_D2,
v_zero_Dtrf, m1, m2,m3, m4, IX, IY, IZ, IW, Lequiv, NTS
var i i_iequi, i_vequi, i_ideviat, i_zero_D2, i_zero_Dtrf,
i_I1out, i_I3out
values
vilf
vvout
vvin
vDon
vDtrf
vD2
{
=
=
=
=
=
=
v(ilf)v(com)
v(vout)v(com)
v(vin)v(com)
v(Don)v(com)
v(Dtrf)v(com)
v(D2)v(com)
Lequiv = Lf + Llk/N**2
NTS
m1
m2
m3
m4
=
=
=
=
=
N*Ts
(vvin/Nvvout)/Lequiv
vvout/Lequiv
vvout/Lf
vvin*N/Llk
if ( vD2 >= 0 & vD2 <= 1vDon ) {
else {
NTS
}
if ( vD2 <= 0 ) {
vD2 = 0
199
=
N*Ts
}
else {
vD2 = 1vDon
}
}
if
( vilf > m1*vDtrf*Ts/2  m1*vDtrf > m2*(1vDon) ) {
AA = (m3+m1)
BB = m4vDoff*(2*m1
m3)+m3*vDon
CC = vDoff*(m2*vDoff+m3*vDon)m4*vDon+2*vilf/Ts
v_zero_Dtrf = AA*vDtrf**2 BB*vDtrf  CC
vDoff
vDch
IY
IX
IW
IZ
=
=
=
=
= 1  vDon
= vDon  vDtrf
(m4m3)*vDch*TS/2
IY + m1*vDtrf*TS
IX  m2*vDoff*TS
IY + m3*vDch*TS
v_vequiv = vvin*vDtrf/N
v_iequiv = ((IZ+IY)*vDch/2+(IY+IX)*vDtrf/2)/N
v_ideviat = (IY+IY)*vDch/2
v_zero_D2 = TS*vD2*m2  IX
}
else {
v_zero_D2 = TS*vD2*m2*(vDtrf+vD2)2*vilf
v_iequiv = vilf*vDtrf/(vDtrf+vD2+1e10)/N
v_ideviat =0
v_vequiv = vvin*vDon/(vDon+vD2+1e10)/N
}
}
# end of values section
200
equations {
i(zero_D2>com) += i_zero_D2
i_zero_D2 : v(zero_D2)  v(com) = v_zero_D2
i(zero_Dtrf>com) += i_zero_Dtrf
i_zero_Dtrf : V(zero_Dtrf)  v(com) = v_zero_Dtrf
i(i_equiv>com) += i_iequi
i_iequi : v(i_equiv)  v(com) = v_iequiv
i(i_deviat>com) += i_ideviat
i_ideviat : v(i_deviat)  v(com) = v_ideviat
i(v_equiv>com) += i_vequi
i_vequi : v(v_equiv)  v(com) = v_vequiv
i(I1out>com) += i_I1out
i_I1out : v(I1out)  v(com) = IX
i(I3out>com) += i_I3out
i_I3out : v(I3out)  v(com) = IY
}
}
#
end of equations section
# end of template body
201
C
Analysis and Design Procedure of Saturable ReactorBased ZeroVoltage ZeroCurrent Switched, FullBridge PWM Converter
and Saber Template for its Average Model
C1.
Introduction
This appendix presents general design procedure for the high power, high
performance ZVZCSFBPWM converter.
Verification of design procedure is performed through both numerical solution of
exact steadystate nonlinear equations and experimental implementation of a practical
design example. The latter corresponds to a specific application: 10 kW, threemodule,
dcdc system operating at 100 kHz.
C2.
Review of Steady State Operation
Fig. C1 shows major topological stages for steady state operation of the ZVZCS
converter, i.e. Blocking, Charging, Transfer, Resetting and Off, whose characteristics are
summarized below.
Blocking Stage. Starts at t0 when Vin is applied between nodes a and b, and ends at
t1 when the saturable reactor stops blocking any current. On the primary side, the sum of
input voltage and the blocking capacitor voltage determines the rate of change of flux in
the saturable reactor, while on the secondary side, the output voltage (assumed constant
throughout the appendix) determines rate of change of current through the filter inductor,
Lf.
Charging Stage. Starts at t1 when current begins to flow on primary side and ends
at t2 when primary current equals reflected filter inductor current. Secondary side
conditions remain the same as in the previous stage.
Transfer Stage. Starts at t2 after primary current equals reflected filter inductor
current with transformer in normal operation, and ends at t3 when Vab becomes zero.
Resetting Stage. Starts at t3 when Vab becomes zero and ends at t4 when primary
current becomes zero. Once again primary and secondary side are independent from one
another.
Off stage. Starts at t4 when primary current becomes zero and saturable reactor
takes all blocking capacitor voltage as its flux rate of change, and ends at Ts when Vab
becomes Vin.
202
S1
Vin
S3
Lf
+
L s Cb Llk
+
a

+
Vs


b
Ip
Vcb
S2
N:1
S4
S2 , S3
Off
Resetting
S2 , S 4
Transfer
Blocking
Charging
S1 , S4
V
Vab
D on ⋅ T s
D on ⋅ T s
m2
I
p
in
Vcpk
V cb
I
If
m1
I
p
2
N ⋅ m2
I 3f
m4
f
m4
I bus
m3
I 3p
I 2f
I
I 4f
f
Vs
Vo
t0 t1 t2
t3
t4
t5
t o + Ts
to
Fig. C1. ZVZCS converter and typical waveforms.
203
t
+

Vo
For each stage, nonlinear equations relating initial and final values of the state
variables can be written. In order to form a complete set of equations two additional
equations are required: one including output power and one describing filter inductor
current ripple. This set, fully described in Equation Set I, will prove very useful later in
this work for development and verification of the dc model.
C3.
Design Procedure
Having high closedloop bandwidth as a major requirement forces the switching
frequency to be very high. Since the ZVZCS topology is of forward type, its smallsignal
loopgain bandwidth can be expected up to one fifth of effective switching frequency. In
multimodule systems with interleaving the effective switching frequency is equal to the
product of the number of parallel modules and the frequency of each module.
After switching frequency selection, converter voltage and current levels will
determine the choice of semiconductor devices. Voltage stress for diodes on the
secondary side will mainly depend on transformer turns ratio and rectifier configuration
(center tap or fullbridge), as well as voltage ringing. The latter is due to diode reverse
recovery characteristics and its interaction with parasitics and snubbers.
In the following design procedure it is assumed that the line and load ranges are
known quantities and that the filter inductor current ripple and output voltage ripple are
specified.
Design of the ZVZCS converter involves complex interactions between device
characteristics, circuit parameters, and operating conditions. Therefore, the design has to
start from several assumptions or estimates which are then iteratively corrected as the
design proceeds. Let us first define dutycycles of different operating stages in Fig. C1 as:
t 3 − t0
Ts
,
(C.1)
apparent:
D=
blocking:
Dblk =
t1 − t0
Ts
,
(C.2)
charging:
Dch =
t 2 − t1
Ts
,
(C.3)
transfer:
Dtrf =
t3 − t2
Ts
,
(C.4)
resetting:
Drs =
t4 − t3
Ts
,
(C.5)
off:
Doff =
Ts − t 4
Ts
.
(C.6)
204
Although the primary circuit is operated with apparent dutycycle, D, the
secondary dutycycle, Dtrf, is smaller by the loss of dutycycle, Dblk+Dch. During transfer
stage, the secondary rectifier output voltage is equal (VinVcb)/N. Since the average value
of the blocking capacitor voltage is approximately zero during this time interval, the
output voltage is very closely given by
Vo =
Vin ⋅ Dtrf
N
.
(C.7)
The main design parameters are: transformer turns ratio, N, blocking capacitor
value, Cblk, and saturable inductor blocking capability. The first major assumption in the
design will be that it is desirable to have N as large as possible in order to minimize the
voltage rating of the secondary diodes as well as primary current peak value. Therefore it
is desirable to use maximum possible value of the transfer dutycycle, Dtrfx. A reasonable
assumption for the first iteration could be
Dtrfx=0.8,
(C.8)
which leaves 10% for the minimum off dutycycle, Doffx, in order to provide sufficient
control authority during transients, and 10% for the sum of Dblk+Dch+Drs.
Second assumption that has to be made is the desired value of the peak blockingcapacitor voltage Vcpk. Small values of Vcpk will increase the resseting time (transformer
leakage inductance is reset only by Vcpk) which will increase the primary current rms
value and limit maximum value of Dtrf. Large values of Vcpk will increase secondary
diode voltage rating, (Vin+Vcpk)/N, and decrease the duration of the charging stage which
will aggravate the secondary diode reverse recovery problems. Empirically determined
reasonable choice was found to be
Vcpk ≤ 0 .2 ⋅Vin .
(C.9)
With assumptions (C.8) and (C.9) the first iteration of the design can be initiated.
The transformer turns ratio can be found from as
N =
Vin min
Vo
⋅ Dtrfx .
(C.10)
Knowing N, Dtrfx, Vo, Ilf, and switching frequency provides sufficient information
for the transformer design. Once the transformer is designed, its leakage inductance, Llk,
can be estimated or measured. The transformer should be designed with minimum
leakage in order to increase the frequency of the ringing in the secondary caused by the
diode reverse recovery, so that it can be more easily suppressed with snubbers.
205
Blocking capacitor, Cblk , is therefore estimated at low line and full load conditions
[C11] by
I lf max ⋅ Dtrfx ⋅ Ts
Cblk =
.
2 ⋅ N ⋅ Vcpk
(C.11)
ZCS operation in steady state requires voltsecond blocking capability of saturable
reactor to be greater than the product Ts ⋅ Vcpk ⋅ Doff at high line and full load conditions.
Thus, the saturation flux of Ls should be
φ sat >
Doff max ⋅ Ts ⋅Vcpk
2 ⋅ N sr
.
(C.12)
where Nsr is the number of turns in Ls. However, ZCS operation during current limiting
situations demands higher voltsecond values from the saturable reactor since the product
Ts ⋅ Vcpk ⋅ Doff becomes much larger than that in (C.12). Furthermore, should saturable
reactor allow oscillation between Llk and Cblk during off stage chaotic operation can occur
and lead to transformer saturation. Therefore, a safe value for the saturation flux of Ls
could be chosen as
φ sat =
Ts ⋅Vcpk
2 ⋅ N sr
.
(C.13)
At this moment the design should be checked against the original assumptions.
so that
During the resetting stage, the primary current reduces with the slope of Vcpk/Llk,
Drs =
(I
lf
)
+ ∆I lf ⋅ Llk
N ⋅ Ts ⋅Vcpk
,
(C.14)
where ∆I lf is the filter inductor current ripple specification.
During charging stage, the primary current increases with the slope of
(Vin+Vcpk)/Llk, and hence
Dch =
(I
lf
)
− ∆I lf ⋅ Llk
(
N ⋅ Ts ⋅ Vin + Vcpk
)
.
(C.15)
During off time the primary current is kept at zero by the saturable inductor Ls
with the voltage across it equal to Vcpk. In the following blocking stage, the voltage across
Ls increases to Vin+Vcpk so that the blocking stage dutycycle can be found as
206
Dblk =
2 ⋅ φ sat
1
⋅
− Doff ⋅ Vcpk
Vin + Vcpk N sr ⋅ Ts
(C.16)
where it is assumed that
Doffx=0.1.
(C.17)
Now, the assumption (A.8) can be verified against
Dtrfx = 1  Drs  Dch  Doffx  Dblk .
(C.18)
Additionally, in order to assure minimum turnon loss in the lagging leg, i.e.
complete zerocurrent turnoff, duration of off stage must be longer than the switch turnoff time [C11]. A reasonable assumption could be
Drs = 1.5 ⋅
Toff + Ttail
,
Ts
(C.19)
where Toff and Ttail are IGBT parameters for full load, and Ttail ≈ 0 for MOSFETs.
If there is only small discrepancy between the assumptions (C.8) and (C.19) and
the results (C.18) and (C.14), it usually can be easily adjusted by changing the values of
Cblk and Vcpk. However, large differences may require changes in the transformer design
(N and Llk), and even change of the switching frequency or selection of active devices.
The design of the output filter is quite straightforward. Lf is normally determined
by current ripple specifications unless very strong output impedance and large signal
requirements make it irrelevant. Considering the first one, Lf must satisfy
Lf ≥
(
Vo ⋅ 1 − Dtrfx
2 ⋅ ∆I lf
)− L
lk
N2
.
(C.20)
Filter capacitor is normally calculated from voltage ripple requirements but
stringent output impedance specifications might override them. Assuming the former as
determining factor, its value is given by
Cf =
∆I lf ⋅ Ts
2
⋅ ∆Vo
2 ⋅ module
207
,
(C.21)
where ∆Vo is peak to peak output voltage ripple and module is the number of paralleled
interleaved modules.
It is worth noting that if the output voltage were to vary over a wide range,
additional conditions, listed in Table C1, will have to be considered in the design
procedure.
Table C1. CONDITIONS FOR PARAMETER SELECTION
Transformer
Turns Ratio
Blocking
Capacitor
Saturable
Reactor
Filter Inductor
Li
ne
Lo
w
Lo
w
Hi
gh
Output
Voltage
High
High
Low
Output
Current
Maximu
m
Maximu
m
Maximu
m
V2
max of Vo − o ⋅ N
Vin
Example: The ZVZCS converter shown in Fig. C1 is designed for the following
specifications
Vin : 280 − 480 V ,
Vo =33 V ,
Po = 3.3 kW ,
∆I f ≤ 30 A , ∆Vo ≤ 20 mV, f s = 100 kHz . .
Using the design procedure given above, following components are selected:
φ sat ⋅ N sr
C3.
N = 6 , Llk = 1µH, Cblk = 1µF,
= 60 µV − s, L f = 2 µH , C f = 200 µF.
DC Analysis
As stated above, dc voltage conversion ratio for the ZVZCS converter is almost
entirely determined by transformer turns ratio and transfer dutycycle. This is verified by
calculating the voltage conversion ratio, for the converter parameters in the above
example, using the exact nonlinear steadystate equations given in Equation Set I. As can
208
be seen from Fig. C2, the ratio is practically independent from input voltage and output
power levels. It is interesting to note that this is true even though the blockingcapacitor
peak voltage and peak primary current vary considerably with input voltage and output
power, as shown in Fig. C3. The same figure also compares the results obtained by using
approximate equations in Equation Set III with those obtained from exact nonlinear
equations in Equation Set I. As can be seen, at least for the numerical values from the
example, there is very small disagreement between the two sets.
Therefore, the dc model is the same as buck converter model except that the
switch dutycycle (named here apparent dutycycle, D) is replaced with the transfer dutycycle, as shown in Fig. C4. Using simplified equations, it is derived in Equation Set II
that the transfer dutycycle is given by
Dtrf =
D ⋅ Vin ⋅ Ts − 2 ⋅ φ sat ⋅ N sr −
Vin ⋅ Ts
2 ⋅ Llk
⋅ I lf
N
( 1 − D) ⋅ Ts2 ⋅ I
−
2 ⋅ N ⋅ Cblk
(C.22)
lf
It follows from (C.24) that the presence of Ls, Llk, and Cblk, introduces
feedforward from Vin and feedback from Ilf into the openloop model of the ZVZCS
converter, similarly as in the ZVSFB converter [V5].
However, unlike in the ZVS, the inductor current feedback in the ZVZCS
converters can be positive. From (C.22) if
( 1 − D) D −
Llk ⋅ Cblk
2 ⋅ φ sat ⋅ N sr
> 2⋅
Vin ⋅ Ts
Ts
(C.23)
the transfer dutycycle increases with the inductor current, resulting in positive feedback.
Since Llk and Cblk are much smaller in ZVZCS than in ZVS converters, condition (C.23)
is satisfied in most cases. It is also important to note that (C.23) is a conservative
condition due to the approximations used in the estimate for Vcpk, and described in
Equation Set II.
The above phenomenon can be further explored by analyzing the loss of dutycycle,
D − Dtrf = Dblk + Dch ,
(C.24)
for the ZVZCS converter. Fig. C5 shows dependence of the blocking and charging dutycycles on the output power, i.e. average filter inductor current. Even though increase in
duration of the charging stage takes place as expected and confirmed by Fig. C5, use of a
lower Cblk value in the ZVZCS converter, as compared to that in the ZVS converter,
allows a strong rise in Vcpk with Po to take place, as it is clearly seen in Fig. C3. This in
209
turn makes the product Vcpk ⋅ Doff ⋅ Ts larger, which leads to a reduction in blocking stage
duration, since saturablereactor voltsecond blocking capability is constant. At the end,
this reduction counteracts for the increase in charging stage duration and produces the
reduction in dutycycle loss. The size of that reduction will strongly depend on blocking
capacitor value and saturable reactor voltsecond blocking capability. Furthermore, it is
possible to have increase in dutycycle loss for some component values, especially when
they resemble those used in the ZVS converter.
C4.
Experimental Results
Design values from the example were used to build a 10 kW, threemodule, dcdc
power converter operating at 100 kHz with current sharing and interleaving.
With three modules working in parallel, the experimental primary current
waveforms for low line and 40% load, and high line and 60% load conditions, are shown
in Fig. C6 where excellent current sharing is clearly observed. This is achieved through
simple and fast current injection control together with very good repeatability of
transformer characteristics provided by printedcircuitboardtype windings. This control
also provides the damping required to achieve as large closedloop bandwidth as possible
[R4].
Fig. C7 shows Bode plots of voltage loopgain transfer function for the threemodule power system operating at 60% load and Vin = 350 V, where crossover frequency
is about 25 kHz. Each module has its own local current loop and their reference is
provided by a common voltage loop.
The most severe problem in the converter operation is reverse recovery of the
secondary diodes, as can be clearly seen in Fig. C6. Since the leakage inductance is so
small, the slope of the rectifier current reversal during charging stage is very steep.
Therefore, rectifier snubber design and its layout are extremely important when dealing
with reverse recovery effects at high currents. Fig. C8 shows voltage waveforms across
one of the rectifiers for two different snubber layouts, Vin=400V, and 100 A load. The big
improvement in peak reduction comes from having the snubber placed right on top of
rectifier which minimizes parasitics in the snubber itself. Even though this made duration
of transfer stage in the primary side look longer, its duration on the secondary side
followed predictions very closely.
210
0.8
0.55
D trf =0.8
D trf =0.5
0.5
0.7
0.45
0.6
D trf =0.6
N Vo
V in
0.4
D trf =0.375
N Vo
V in
0.35
0.5
0.3
0.4
Dtrf =0.25
Dtrf =0.4
1000
2000
3000
0.3
1000
0.25
2000
Po
3000
0.2
Po
(a) low line
(b) high line
Fig. A2. Voltage conversion ratio.
40
40
D=0.775
D=0.416
35
35
V
Cpk
30
30
V Cpk
25
25
20
20
Ipripk
I pripk
500
1000
1500
2000
2500
3000
15
15
10
10
3500
5
Po
500
1000
1500
2000
2500
3000
3500
5
Po
(a) low line
(b) high line
Fig. C3. Blockingcapacitor peak voltage, peak primary current for exact (solid) and
approximate (dotted) equations.
211
Lf
+
+
Vin
N
Vo
1 : Dtrf
Fig. C4. Dc model for ZVZCS converter.
7
7
D=0.775
D=0.416
6
6
5
5
4
4
D blk
D blk
3
3
2
1
D ch
500
1000
1500
2
1
D ch
2000
2500
3000
3500
0
500
1000
1500
2000
2500
3000
3500
0
Po
Po
(a) low line
(b)high line
Fig. C5. Dutycycles of blocking and charging stages for exact (solid) and approximate
(dotted) equations.
212
Horizontal : 2 µs / div
Vertical : 5A / div
(a) Low line, 40% load
(b) High line, 60% load
Fig. C6. Experimental primary currents from 3module dcdc power system with
interleaving.
Magnitude (db)
80
60
0
40
Phase (deg)
45
90
135
180
225
0.1
1
10
100
Frequency (kHz)
Fig. C7. Voltage loopgain for the 3module dcdc power system at Vin=350 V and 6 kW
resistive load.
213
300 V
Normal
layout
0V
300 V
Optimal
layout
0V
Horizontal: 50 ns /div
Fig. C8. Voltage across rectifier for same snubber values but different layouts, at
Vin=400 V and 100 A load.
214
C5.
Nomenclature
Vin, Vo: input and output voltages
Ilf : average output (filter inductor) current
Po: output power
Llk, Lf : primary leakage and filter inductors
Dblk, Dch, Dtrf, Drs, Doff : average value for blocking, charging, transfer, resetting and off
dutycycles.
D: average apparent dutycycle
Vcb1, Vcb2, Vcb3, Vcb4: blockingcapacitor voltage at t1, t2, t3, and t4 in Fig. 1, respectively
Ip2, Ip3: primary current at t2 and t3 in Fig. 1, respectively
Vcpk: estimate of blockingcapacitor peak voltage
φ sat : saturation flux of saturable inductor
∆φ off : change of flux in saturable reactor during off stage.
∆φ blk : change of flux in saturable reactor during blocking stage
N sr : turns in saturable reactor
N : primary to secondary turns ration
fs: switching frequency
Ts : switching period
Llk: primary leakage inductance
Cblk: blocking capacitor
Z1, ω1 : characteristic impedance and resonant frequency during charging and resetting
stages.
Z2, ω2 : characteristic impedance and resonant frequency during transfer stage
C6.
Equation Set I
SteadyState Boundary Equations for Topological Stages
Blocking Stage:
Dblk ⋅ Ts ⋅ (Vin + Vcb1 )
N sr
(CI1)
Vin +Vcb1
Z1 ⋅ sin(ω 1 ⋅ Dch ⋅ Ts )
(Ci2)
∆φ blk =
Charging Stage:
I p2 =
Vcb 2 = (Vcb1 + Vin ) ⋅ cos(ω 1 ⋅ Dch ⋅ Ts ) − Vin
Z1 =
Llk / Cblk
ω1 = 1/
215
Llk ⋅ Cblk
(CI3)
(CI4)
(CI5)
Transfer Stage:
(
I p 3 = I p 2 ⋅ cos ω 2 ⋅ Dtrf ⋅ Ts
)
+
Vin − N ⋅ Vo + Vcb 2
⋅ sin ω 2 ⋅ Dtrf ⋅ Ts
Z2
(
(
Vcb3 = (Vcb2 +Vin − N ⋅Vo ) ⋅ cos ω2 ⋅ Dtrf ⋅ Ts
)
)
(
−(Vin − N ⋅Vo ) − I p2 ⋅ Z2 ⋅ sin ω2 ⋅ Dtrf ⋅ Ts
4
Z 2 = ⋅ Llk + N 2 ⋅ L f / Cblk
3
4
3
(CI6)
)
(CI7)
(CI8)
ω 2 = 1 / ⋅ Llk + N 2 ⋅ L f ⋅ Cblk
(CI9)
(It is assumed that secondary leakage inductance reflected to the primary is half of Llk.)
Resetting Stage:
Vcb3
⋅ sin(ω 1 ⋅ Drs ⋅ Ts ) = I lk 3 ⋅ cos(ω 1n ⋅ Drs ⋅ Ts )
Z1
(CI10)
Vcb 4 = −Vcb1 = Vcb 3 ⋅ cos(ω 1 ⋅ Drs ⋅ Ts )
− I lk 3 ⋅ Z1 ⋅ sin(ω 1 ⋅ Drs ⋅ Ts )
(CI11)
Off Stage:
∆φ off =
Vcb1 ⋅ Doff ⋅ Ts
(CI12)
N sr
Filter Inductor Current Ripple:
(
)
Vo ⋅ 1 − Dtrf ⋅ Ts
Lf +
Llk
N2
216
(
)
= I p3 − I p2 ⋅ N
(CI13)
Output Power:
(
I p 3 ⋅ sin ω 2 ⋅ Dtrf ⋅ Ts
Po
= N I p 2 ⋅ 1 − Dtrf +
Vo
ω 2 ⋅ Ts
(
)
+
) + V ⋅ (1 − D )
2⋅(L )
o
2
trf
f
[
(
N ⋅ (Vin − N ⋅Vo + Vcb 2 ) ⋅ 1 − cos ω 2 ⋅ Dtrf ⋅ Ts
Z 2 ⋅ ω 2 ⋅ Ts
)]
(CI14)
Saturable Reactor Total Flux Change:
(CI15)
2 ⋅ φ sat = ∆φ off + ∆φ blk
C7.
Equation Set II
Average Dtrf in SteadyState
Simplified equations for computation of average Dtrf in terms of D after neglecting
inductor current ripple, Vcpk with respect to Vin, and contributions of charging and
resetting stages to Vcpk.
Doff = 1 − ( D + Drs )
(CII1)
D = Dblk + Dch + Dtrf
(CII2)
2 ⋅ φ sat =
Dch =
Drs =
Vcpk =
(D
off
Llk ⋅ I lf
N ⋅Vin ⋅ Ts
Llk ⋅ I lf
N ⋅Vcpk ⋅ Ts
I lf ⋅ Dtrfx ⋅ Ts
2 ⋅ N ⋅ Cblk
217
)
⋅Vcpk + Dblk ⋅Vin ⋅ Ts
N sr
(CII3)
(CII4)
(CII5)
(CII6)
Solving (CII1)(CII6)gives
Dtrf =
D ⋅Vin ⋅ Ts − 2 ⋅ φ sat ⋅ N sr −
( 1 − D) ⋅ Ts2 ⋅ I
−
Vin ⋅ Ts
C8.
2 ⋅ Llk
⋅ I lf
N
2 ⋅ N ⋅ Cblk
(CII7)
lf
Equation Set III
Approximate SteadyState Equations
2 ⋅ φ sat =
[D
off
(
⋅ Vcpk + Dblk ⋅ Vin + Vcpk
N sr
Dch =
Drs =
Dtrf =
∆ ilf =
(
Llk ⋅ I lf − ∆I lf
(
)
)
N ⋅ Vin + Vcpk ⋅ Ts
(
Llk ⋅ I lf + ∆I lf
)
N ⋅Vcpk 2 ⋅ Ts
Vo ⋅ N
Vi
(
)] ⋅ Ts
(CIII1)
(CIII2)
(CIII3)
(CIII4)
)
Vin ⋅ 1 − Dtrf ⋅ Dtrf ⋅ Ts
L
N ⋅ L + ⋅ lk2
N
Po = Vo ⋅ I lf
218
(CIII5)
(CIII6)
C9.
Listing of Saber templates for New Model of ZVZCSFB PWM
Converter
C9.1
Template 1.
This template calculates charging and resetting dutycycles, average
controlledvoltage source, peak blovckingcapacitor voltage and flux constraint
equation.
element template dchrsdeviaveffcpkzero com In1 In2 In3 In4
In5 In6 In7 in8 Out1 Out2 Out3 Out4 Out5 Out6 = Ts, Lf,
Llk, Cblk, N, phi_sat
electrical com, In1, In2, In3, In4, In5, In6, In7, In8,
Out1, Out2, Out3, Out4, Out5, Out6
number Ts, Lf, Llk, Cblk, N, phi_sat
{
val v v1, v2, v3,v4, v5, v6, v7, v8, ilf, Dtrf, Doff, Dblk,
ipk, ivall, delta_ilf, vin, vcpk, Lequiv, Zo, Wo, Dch, Drs,
Idevia, veff, zero_satu,
v_out1, v_out2, v_out3, v_out4, v_out5, v_out6
var i i_Out1, i_Out2, i_Out3, i_Out4, i_Out5, i_Out6
values {
v1
v2
v3
v4
v5
v6
v7
v8
=
=
=
=
=
=
=
=
v(In1)v(com)
v(In2)v(com)
v(In3)v(com)
v(In4)v(com)
v(In5)v(com)
v(In6)v(com)
v(In7)v(com)
v(In8)v(com)
Lequiv = Lf + Llk/N**2
Zo
Wo
=
=
(Llk/Cblk)**0.5
1/(Llk*Cblk)**0.5
219
ilf = v1
Dtrf = v2
ipk = v3
ivall = v4
delta_ilf = v5
vin
= v6
Doff = v7
Dblk = v8
vcpk = ilf*Dtrf*Ts/(2*N*Cblk) +
(ilf+delta_ilf/2)*Llk/(2*N*Ts)
Dch = (ilfdelta_ilf/2)*Llk/(vin+vcpk)/N/Ts
Drs = Llk*(ilf+delta_ilf/2) / (vcpk*N*Ts+1e10)
Idevia = (1  Dtrf)*ilf
veff = vin*Dtrf/N + ilf*Llk/(2*N**2*Ts)
zero_satu = phi_sat/Ts  Doff*vcpk  (vin + vcpk)*Dblk
v_out1
v_out2
v_out3
v_out4
v_out5
v_out6
}
=
=
=
=
=
=
Dch
Drs
Idevia
veff
vcpk
zero_satu
# end of values section
equations {
i(Out1>com) += i_Out1
i_Out1 : v(Out1)  v(com) = v_Out1
i(Out2>com) += i_Out2
i_Out2 : v(Out2)  v(com) = v_Out2
i(Out3>com) += i_Out3
i_Out3 : v(Out3)  v(com) = v_Out3
i(Out4>com) += i_Out4
i_Out4 : v(Out4)  v(com) = v_Out4
220
i(Out5>com) += i_Out5
i_Out5 : v(Out5)  v(com) = v_Out5
i(Out6>com) += i_Out6
i_Out6 : v(Out6)  v(com) = v_Out6
}
}
#
end of equations section
# end of template body
C9.2
Template 2.
This template calculates blocking and off dutycycle, and peak and valley
values for primary current.
element template pkvaldeltablkoff com In1 In2 IN3 In4 In5
In6 In7 Out1 Out2 Out3 Out4 Out5 = Ts, Lf, Llk, Cblk, N,
phi_sat
electrical com, In1, In2, IN3, In4, In5, in6, iN7, Out1,
Out2, Out3, Out4, Out5
number Ts, Lf, Llk, Cblk, N, phi_sat
{
val v v1, v2, v3, v4, v5, v6, v7, ilf, vin, vout, Don, Dch,
Drs, Dtrf, Dblk, Doff, delta_up, delta_dwn, delta_ilf,
Lequiv,
Zo, Wo, ipk, ivall, v_out1, v_out2, v_out3, v_out4,
v_out5
var i i_Out1, i_Out2, i_Out3, i_Out4, i_Out5
values {
v1 = v(In1)v(com)
v2 = v(In2)v(com)
221
v3
v4
v5
v6
v7
=
=
=
=
=
v(In3)v(com)
v(In4)v(com)
v(In5)v(com)
v(In6)v(com)
v(In7)v(com)
Lequiv = Lf + Llk/N**2
Zo
Wo
=
=
(Llk/Cblk)**0.5
1/(Llk*Cblk)**0.5
vin = v1
vout = v2
ilf = v3
Dtrf = v4
Don = v5
Dch = v6
Drs = v7
delta_up = (vin/Nvout)*Dtrf*TS/Lequiv
delta_dwn = vout*(1Dtrf)*Ts/Lf
delta_ilf = delta_up
Dblk = Don  Dch  Dtrf
Doff = 1  Don  Drs
ipk = ilf + delta_ilf/2
ivall = ilf  delta_ilf/2
v_out1
v_out2
v_out3
v_out4
v_out5
}
=
=
=
=
=
ipk
ivall
delta_ilf
Dblk
Doff
# end of values section
equations {
i(Out1>com) += i_Out1
i_Out1 : v(Out1)  v(com) = v_Out1
222
i(Out2>com) += i_Out2
i_Out2 : v(Out2)  v(com) = v_Out2
i(Out3>com) += i_Out3
i_Out3 : v(Out3)  v(com) = v_Out3
i(Out4>com) += i_Out4
i_Out4 : v(Out4)  v(com) = v_Out4
i(Out5>com) += i_Out5
i_Out5 : v(Out5)  v(com) = v_Out5
}
} # end of equations section
# end of template body
223
D
Modified Equations for Cases 2 and 3 of QSSZVZCS
ThreePhase Buck Rectifier Operation and for
Compensated First DutyCycle for Case 1
D1.
Modified Constraint Equations for Case 2
Vline1 + Vcpk
I 2p =
LLk
(t 2 − t1 )⋅ = (m1) ⋅ (Dch1 ⋅ Ts ) ,
I 2f ≠ I 2p ⋅ N ,
(D1.9)
(D1.10)
I 3f = I 3p ⋅ N ,
(D1.10.a)
d 1 ⋅ Ts = (t 2 − t 0 ) == (Dblk + Dch1 ) ⋅ Ts .
(D1.11)
− V0
I −I =
Llk 2 + L f
N
⋅ (t 3 − t 2 )⋅ = ( N ⋅ m4 ) ⋅ (Dch 2 ⋅ Ts ) ,
(D1.12)
Vac
− V0
N
I 4f − I 3f =
Llk 2 + L f
N
⋅ (t 4 − t 3 )⋅ = ( N ⋅ m3 ) ⋅ (Dtrf 2 ⋅ Ts )
(D1.13)
f
3
f
2
t 5 − t 4 = Dres ⋅ Ts =
∆ φoff =
Ip
Llk
1
⋅ arcsin 4 ⋅
V
Cblk
LLk ⋅ C Blk
Cpk
Vcpk ⋅ (1 − d 1 − d 2 − Dres ) ⋅ Ts
N sr
∆ φblk = 2 ⋅ φ sat − ∆ φoff ,
224
,
.
(D1.14)
(D1.15)
(D1.16)
∆ Vc −trf =
I L ⋅ (Dtrf 2 )⋅ Ts
(I ) ⋅ L
=
N ⋅ I ⋅ (D )⋅ T
f 2
4
∆ Vc −res
L
Vcpk =
IL =
(I
f
5
[
(D1.17)
N ⋅ Cblk
lk
trf 2
∆ Vc−trf + ∆ Vc−res
2
(
,
(D1.18)
s
.
(D1.19)
)
(
V
− I 4f = 0
L
f
)
⋅ (1 − Dtrf 2 )⋅ Ts = m4 ⋅ (1 − Dtrf 2 )⋅ Ts ,
Vs 1 = 0
Vline 2 ⋅ Dtrf 2
N
L
V
⋅ L f + V0 ⋅ lk2 + cb ⋅ L f
N
N
Llk
+ Lf
N2
Vcb = Vcpk −
I phase 2
(I
=
p
2
)
(D1.20)
(D1.21)
(D1.22)
Vline 2 + Vcb
L
⋅ L f + V0 ⋅ lk2
N
N ,
Vs 2 =
Llk
+ Lf
N2
Vs =
)]
1
⋅ Dtrf 2 ⋅ I 4f + I 3f + (1 − Dtrf 2 )⋅ I 5f + I 4f ,
2
I L ⋅ (Dtrf 2 )⋅ TS
2 ⋅ N ⋅ Cblk
I phase1 =
I 2p
⋅ Dch1
2
(
)
(D1.23)
⋅ (Dtrf 2 )
(D1.24)
.
(D1.25)
+ I 3p
I 3p + I 4p
⋅ Dch 2 +
⋅ Dtrf 2 .
2
2
225
(D1.26)
(D1.27)
D2.
Modified Constraint Equations for Case 3
Vline1 + Vcpk
N sr
∆φblk = (t1 − t0 ) ⋅
+ Vcpk
V
+ (t 2 − t1 ) ⋅ line 2
=
N sr
+V
V +V
V
(Dblk 1 ⋅ Ts ) ⋅ line1 cpk + (Dblk 2 ⋅ Ts ) ⋅ line 2 cpk
N sr
N sr
I 2p = 0 ,
,
(D2.8)
(D2.9)
I 2f ≠ I 2p ⋅ N ,
(D2.10.a)
I 3f ≠ I 3p ⋅ N ,
(D2.10.b)
I 4f = I 4p ⋅ N ,
(D2.10.c)
d 1 ⋅ Ts = (t1 − t0 ) == (Dblk 1 ) ⋅ Ts .
(D2.11.a)
d 2 ⋅ Ts = (t 3 − t1 ) == (Dblk 2 + Dch 3 + Dtrf 3 )⋅ Ts .
(D2.11.b)
− V0
I −I =
Llk 2 + L f
N
⋅ (t 3 − t 2 )⋅ = ( N ⋅ m4 ) ⋅ (Dch 3 ⋅ Ts ) ,
(D2.12)
Vac
− V0
N
I −I =
Llk 2 + L f
N
⋅ (t 4 − t 3 )⋅ = ( N ⋅ m3 ) ⋅ (Dtrf 3 ⋅ Ts )
(D2.13)
f
3
f
4
f
2
f
3
t 5 − t 4 = Dres ⋅ Ts =
∆ φoff =
Ip
Llk
1
⋅ arcsin 4 ⋅
LLk ⋅ C Blk
VCpk Cblk
Vcpk ⋅ (1 − d 1 − d 2 − Dres ) ⋅ Ts
N sr
∆ φblk = 2 ⋅ φ sat − ∆ φoff ,
226
,
.
(D2.14)
(D2.15)
(D2.16)
∆ Vc −trf =
I L ⋅ (Dtrf 3 )⋅ Ts
(I ) ⋅ L
=
N ⋅ I ⋅ (D )⋅ T
f
4
∆ Vc −res
L
Vcpk =
IL =
(I
f
5
[
(D2.17)
N ⋅ Cblk
2
lk
trf 3
∆ Vc−trf + ∆ Vc−res
2
(
,
(D2.18)
s
.
(D2.19)
)
(
V
− I 4f ) = 0
L
f
⋅ (1 − Dtrf 3 )⋅ Ts = m4 ⋅ (1 − Dtrf 3 )⋅ Ts ,
Vs 1 = 0
Vline 2 ⋅ Dtrf 3
N
L
V
⋅ L f + V0 ⋅ lk2 + cb ⋅ L f
N
N
Llk
+ Lf
N2
Vcb = Vcpk −
(D2.21)
I L ⋅ (Dtrf 3 )⋅ TS
2 ⋅ N ⋅ Cblk
(D2.23)
⋅ (Dtrf 3 )
(D2.24)
.
(D2.25)
I phase1 = 0
I phase =
(D2.20)
(D2.22)
Vline 2 + Vcb
L
⋅ L f + V0 ⋅ lk2
N
N ,
Vs 2 =
Llk
+ Lf
N2
Vs =
)]
1
⋅ Dtrf 3 ⋅ I 4f + I 3f + (1 − Dtrf 3 )⋅ I 5f + I 4f ,
2
(
(D2.26)
)
I 3p
I p + I 3p
⋅ Dch 3 + 3
⋅ Dtrf 3
2
2
227
(D2.27)
D3.
Simplified Equations for Compensated First DutyCycle in Case 1
Simplified equations for computation of applied D1 in terms of Dtrf after
neglecting Vcpk with respect to Vin, and contributions of charging and resetting stages to
Vcpk.
Dblk ⋅ Ts ⋅ Vline1
N sr
(1.b)
I L ⋅ Llk
,
N ⋅ Ts
(2.b)
Dtrf 1 = d1 − Dblk − Dch .
(4.b)
∆φblk =
Dch ⋅ Vline1 =
Dres =
Vcpk =
Llk ⋅ I L
N ⋅ Vcpk ⋅ Ts
(7.b)
I L ⋅ (Dtrf 1 + d 2 ) ⋅ Ts
∆φoff =
2 ⋅ N ⋅ Cblk
Vcpk ⋅ Doff ⋅ Ts
N sr
,
(8.b)
(9.b)
2 ⋅ φsat = ∆φoff + ∆φblk .
(10.b)
Doff = 1 − (d1 + d 2 + Dres ) .
(11.b)
Solving this set gives
Dtrf 1 +
d1 =
2 ⋅ φ sat ⋅ N sr I lf Ts ⋅ (1 − d 2 ) ⋅ (Dtrf 1 + d 2 ) 2 ⋅ Llk
−
−
Vin1 ⋅ Ts
⋅N
2 ⋅ Cblk ⋅ Vin1
Ts ⋅ Vin1
I lf ⋅ Ts ⋅ (Dtrf 1 + d 2 )
1−
2 ⋅ Cblk ⋅ Vin1 ⋅ N
where Dtrf 1 = D pri1 is the desired primary dutycycle.
228
(17.b)
VITA
Carlos Eduardo Cuadros O. was born August 3, 1958 in Palmira Colombia. He
received the Ingeniero Electronico degree in 1982 from Pontificia Universidad Javeriana,
Bogota, Colombia, where he was also a research and teaching associate from 1982 to
1985, and a Master of Science in electrical Engineering from Virginia Polytechnic
Institute and State University in 1998.
From 1985 to 1991 he worked for LabVolt Systems, NJ as a Field Engineer in
their Ecuadorian division and from 1999 to 2003 he was a design engineer with Dynamic
Structures and Materials, Franklin, Tennessee.
His current research interest is design, modeling an control of dc to dc, threephase to dc and dc to threephase uni and bidirectional softswitching converters.
229