The x86 Ecosystem Advisory Group led by Intel and AMD recently firmed up the AI Compute Extensions (ACE) specification for optimizing x86 for AI computation tasks around matrix multiplication and the like for machine learning workloads. The cross-vendor ACE extension is ultimately a successor to Intel's Advanced Matrix Extensions (AMX). Posted to the GCC mailing list today by Intel engineers are the initial patches in preparing the compiler support for ACE.

Back in mid-June the x86 Ecosystem Advisory Group published the ACEv1 extension to define matrix multiplication primitives to augment Advanced Vector Extensions (AVX) and scalar code with new capabilities focused on AI/ML workloads:

"The ACE extensions define matrix multiplication primitives that augment AVX and scalar code with new capabilities, adding:

- ACE register state, including tile and block scale registers
- Data processing operations that consume AVX register input and operate on tile register state
- Data move operations to move data between ACE register state and AVX registers
- State and operations for system management

ACE provides tight integration between AVX vectors and ACE tile registers, combining high compute density tile processing operations with the comprehensive data processing features of AVX."

In preparing for future processors supporting ACE, today Intel posted the initial GNU Compiler Collection patches for the AI Compute Extensions. The ACE compiler enablement is in part based on Intel's existing AMX-TILE compiler code and also some AVX-512 elements.

Those interested in this very initial bring-up of ACE for the GCC compiler can find the work on the GCC patches mailing list. Hopefully this initial ACEv1 support makes it into next year's GCC 17 stable compiler release.